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A qualitative model for the programming physics of 90-nm silicided polysilicon fuses is presented. Finding reveals the achievement of an increase in resistance by [10.sup.7] times.

Milke et al. (Contrib Mineral Petrol 142:15-26, 2001) studied the diffusion of Si, Mg and O in synthetic polycrystalline enstatite reaction rims. The reaction rims were grown at 1,000[degrees]C and 1 GPa at the contacts between forsterite grains with normal isotopic compositions and a quartz matrix extremely enriched in [sup.18]O and [sup.29]Si. The enstatite reaction rim grew from the original quartz-forsterite interface in both directions producing an inner portion, which replaced forsterite and an outer portion, which replaced quartz. Here we present new support for this statement, as the two portions of the rim are clearly distinguished based on crystal orientation mapping using electron backscatter diffraction (EBSD). Milke et al. (Contrib Mineral Petrol 142:15-26, 2001) used the formalism of LeClaire (J Appl Phys 14:351-356, 1963) to derive the coefficient of silicon grain boundary diffusion from stable isotope profiles across the reaction rims. LeClaire's formalism is designed for grain boundary tracer diffusion into an infinite half space with fixed geometry. A fixed geometry is an undesired limitation in the context of rim growth. We suggest an alternative model, which accounts for simultaneous layer growth and superimposed silicon and oxygen self diffusion. The effective silicon bulk diffusivity obtained from our model is approximately equal within both portions of the enstatite reaction rim: [D.sub.Si,En.sup.eff] = 1.0-4.3x[10.sup.-16] [m.sup.2] [s.sup.-1]. The effective oxygen diffusion is relatively slow in the inner portion of the reaction rim, [D.sub.O,En.sup.eff] = 0.8-1.4X[10.sup.-16] [m.sup.2] [s.sup.-1], and comparatively fast, [D.sub.O,En.sup.eff] = 5.9-11.6x[10.sup.-16] [m.sup.2] [s.sup.-1], in its outer portion. Microstructural evidence suggests that transient porosity and small amounts of fluid were concentrated at the quartz-enstatite interface during rim growth. This leads us to suspect that the presence of an aqueous fluid accelerated oxygen diffusion in the outer portion of the reaction rim. In contrast, silica diffusion does not appear to have been affected by the spatial variation in the availability of an aqueous fluid.

This work addresses a range of issues on modeling electrothermal microactuators, including the physics of temperature dependent material properties and Finite Element Analysis modeling techniques. Electrical and thermal conductivity are a nonlinear function of temperature that can be explained with electron and phonon transport models, respectively. Parametric forms of these equations are developed for polysilicon and a technique to extract these parameters from experimental data is given. A modeling technique to capture the convective and conductive cooling effects on a thermal actuator in air is then presented. Using this modeling technique and the established polysilicon material properties, simulation results are compared with measured actuator responses. Both static and transient analyzes have been performed on two styles of actuators and the results compare well with measured data. [946] Index Terms--Electrothermal microactuator, modeling thermal actuator, polysilicon material properties.

A simple, one-step LPCVD process was recently reported to allow the repeatable fabrication of polycrystalline silicon (polysilicon) thin films containing through-pores measuring 10-50 nm in diameter, as-deposited, with no additional processing steps required. This paper describes methods for using this one-step porous polysilicon material to quickly and easily fabricate structures of interest to MEMS designers. Among the structures presented are hermetically sealed diaphragms, hollow tube and shell structures, substrate-aligned membranes over one square centimeter in area ('supermembranes'), and permeable fluidic microchannels on silicon and quartz substrates. [887] Index Terms--Encapsulation, filters, hollow shells, low-pressure chemical vapor deposition (LPCVD), membranes, micromachining, permeable polysilicon, porous polysilicon, sealing, thin films.

An investigation is described into the effects of an in-situ hydrogen bake and an ex-situ hydrofluoric acid (HF) etch prior to polysilicon deposition on electrical characteristics of bipolar transistors fabricated with low thermal budget in-situ phosphorus-doped polysilicon emitter contacts. Low value of emitter resistance obtained with a high defect density single-crystal silicon emitter suggests applications involving deep submicron Si bipolar or SiGe heterojunction bipolar transistors (HBT) in circumstances where the thermal budget is constrained.

Research on band-tail parameters is examined in detail, including the development of a polysilicon band-tail model with energy band structure analysis.

Base-broadening effects caused by extrinsic base implantation in SiGe heterojunction bipolar transistors (HBT) can be suppressed by introducing a buried carbon layer. The carbon layer is introduced under the SiGe/Si base prior to epitaxy.

Limits of classical treatment in barrier height determination are examined in terms of the Fowler-Nordheim conduction of polysilicon.

Quantum-mechanical behaviour of charge carriers at the polysilicon/oxide interface was examined.

A high quality polysilicon oxide that combines N20 nitridation and chemical mechanical polishing processes is described.

A thermal actuator to determine polysilicon fracture strength and fatigue is presented.

Polysilicon gate effects on the random dopant induced threshold voltage fluctuations in MOSFET's are examined.

A high-speed capacitive humidity sensor was integrated on a polysilicon heater.

Research is presented concerning the use of fluorescence emission and UV-absorption spectroscopy to determine that the structure of two nonionic polysilanes in aqueous solution takes the form of a random coil which is highly folded.

It has been possible to study the energy transfer in bilayer films made of a highly oriented poly(diethylsilylene) (PDES) layer and a poorly oriented poly(methyloctadecylsilylene) (PMOdS) layer. Electronic energy transfer arises at the interface of the bilayer films from the poorly oriented PMOdS layer to the highly oriented PDES layer.

An experimental and theoretical demonstration of the impact of tunneling currents and channel resistance on the measured gate-to-channel capacitance using long-channel metal oxide semiconductor field effect transistors with sub-20-angstrom gate oxide is presented. A model is derived for the terminal capacitance in terms of tunneling conductance, intrinsic capacitances, measurement frequency and channel length. The model is useful in characterizing a measured extrinsic capacitance fall-off in strong inversion and its relationship with the oxide thickness and channel length of the test structure.

A study was conducted to analyze a lateral type polysilicon field emission triode utilizing standard photolithography and a local oxidation of polysilicon method in a lateral direction. The techniques supported good reproducibility in shaping sharp electrode tips and controlling the short cathode-to-gate inter-electrode distance. Results indicated that the device featured excellent electrical properties.

A study was conducted to analyze the profile and dimension control mechanism in polysilicon gate etching. A two-dimensional etching topography simulator was utilized to carry out the analysis. The reaction times were computed using interactions between incoming ion/radical fluxes. Plasma internal parameters were then modeled as input data of the simulator. In addition, a qualitative guideline was proposed to realize anisotropic etched-profile formation and the dimension difference minimization.

A study was conducted to analyze differences in the temperature of the Fowler-Nordheim emission in metal-oxide semiconductor structures when the injecting electrode is the degenerate polysilicon gate. The temperature dependence of the electron affinity difference between silicon and SiO2 and the barrier height for three oxide thicknesses was examined. Results were numerically determined from the exact integral expression of the Fowler-Nordheim current as functions of temperature.

This paper explores the use of thick glass films as suitable alternatives to CVD oxide films for use as sacrificial, planarization, and passivation layers in polysilicon surface micromachining processes. Such glasses can be spin-coated to produce films up to 20 [[micro]meter] thick in one step and to globally planarize the wafer surface, extending the overall mechanical design capability by enabling additional device structural complexity. Glass optical constants were determined, and the film quality was evaluated using SEM, EDS, XPS, and XRD. The films were found to have low intrinsic stresses and other characteristics desirable for sacrificial layer applications. A glass chemical-mechanical polishing process with 5300-[Angstrom]/min removal rate and acceptable selectivity to polysilicon was developed, along with a wet etch chemistry that preferentially etches the film at 3.24 [[micro]meter]/min without affecting the silicon substrate or the structural polysilicon. The film was used to planarize up to 10-[[micro]meter]-tall topographies associated with surface micromachined features through spin-on and polish-back steps, and was in addition demonstrated to be a viable protective layer for silicon wafers during extended KOH etching in silicon bulk micromachining processes. The glass has stable constituents that do not diffuse or contaminate either the substrate or the device features during the application and firing procedures. Index Terms - Chemical-mechanical polishing (CMP), glass, microactuators, planarization, surface micromachining, thick films.

A physical-based analytical current model of polycrystalline silicon thin-film transitors for circuit simulation that is characterized by temperature dependence, barrier potential at grain boundaries and drain induced grain barrier lowering and the kink effect is introduced. This model includes an accurate model of the kink effect whose parameters can be used in polysilicon thin film transistors with different sizes.

The transient current measurement of polysilicon thin film transistors is examined with particular focus on the presence of an 'overshoot' in the transient response. There is 'capacitance overshoot' when the gate-source capacitance CGS can be greater than the oxide capacitance C(sub OX)WL at low frequency and high voltage. A method for quantifying the transient response is introduced and the impact of the capacitance overshoot is illustrated. The results are discussed.

In comparison with conventional heat treatment, high-temperature rapid thermal annealing (RTA) in a radio frequency (RF) induction-heated system can reduce or eliminate residual stresses in thin films in a few seconds. In this work, changes in the stress level due to the RTA of polycrystalline silicon thin films were studied as a function of annealing time and temperature. The corresponding variations in the microstructure and surface layer of the thin films were experimentally investigated by a variety of analytical tools. The results suggest that the residual stress evolution during annealing is dominated by two mechanisms: 1) microstructure variations of the polysilicon thin film and 2) effects of a surface layer formed during the heat treatment. The fact that the microstructure changes are more pronounced in samples after conventional heat treatment implies that the effects of the formed surface layer may dominate the final state of the residual stress in the thin film. [337] Index Terms - Polysilicon thin films, rapid thermal annealing, residual stress.

In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 [[micro]meter] 64 x 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.

A chemical vapor deposition tetra-ethyl-ortho-silicate oxide which is deposited on the phosphorus in-situ/POCl3 doped polysilicon and applied with N2O rapid thermal annealing is found to have desirable characteristics. These include asymmetric J-E features and a very large charge-to-breakdown of up to 110 C/Cm(super 2) because of the good polysilicon/oxide interface morphology derived by the replacement of POCl3 doping with in-situ doping and the rapid thermal annealing in N2O.

A sticking (stiction) model for a cantilevered beam is derived. This model includes the effect of the bending moment, which stems from stress gradient along the vertical direction of structural polysilicon, and the temperature during the release process. The bending moment due to the stress gradient will play an important role to evaluate antisticking efficiency since liquid tension and surface energy of microstructures tend to become smaller by newly developed antisticking techniques. The effects of stress gradient and temperature were analyzed and verified with surface-micromachined polysilicon cantilevers. By modifying the substrate polysilicon with grain-hole formation technique, the effects of residual stress gradient in polysilicon on stiction could be observed in the condition of low work of adhesion. Index Terms - Grain hole, polysilicon, sticking, stress gradient, surface micromachining.

Research was conducted to identify the effect of rapid thermal annealing on the structural and electrical attributes of poly-Si thin films. In addition, the influence of grain size, grain boundaries and surface roughness on the electrical properties of these films were also examined. The films were grown through the crystallization of a-Si films deposited via rapid thermal low-pressure chemical vapor deposition. Experiments resulted to the formation of large grains characterized by the absence of in-grain defects, low surface roughness and higher Hall mobility.

MOSFET dosimeters incorporating an electrically floating polysilicon gate have been fabricated in a commercial CMOS technology. Charge is placed on the floating gate by tunnelling from a small overlapping injector gate. Subsequent irradiation partially discharges the floating gate, producing a change in threshold voltage which can be used to infer the absorbed dose. No external power source is required during this sensing period. Sensitivities up to 70 [mVGy.sup.-1] (0.7 mV/rad) have been obtained for temperature-compensated matched-pair dosimeters under 60Co gamma irradiation.

Research has established a low field leakage current model which describes low-temperature laser recrystallized polysilicon thin-film transistors. The model is applicable at low drain to source voltage and accounts for active layer length, bias-stress, density-of-states and the effects of leakage current on device active layer thickness. Two-dimensional simulation techniques are discussed.

Research was conducted to examine the effect of supersonic jets on growth, film quality and uniformity using silicon epitaxy as a model system. A comparison was made between the silicon growth from supersonic jets of SiH4 and the growth from supersonic jets of Si2H6. Results demonstrate that at higher substrate temperatures, the high kinetic energy SiH4 jet exhibited a higher growth rate than the low kinetic energy SiH4 jet despite the fact that the flux of the high energy jet had a factor of 8 lower than the flux of the low energy jet.

Research was conducted to examine floating body effects in polycrystalline silicon thin film transistors (TFT) using numerical simulations. Two dimensional simulations were utilized to analyze the kink effect in poly-TFTs which allowed a precise description of the microscopic phenomena occurring in the device. Results indicated that the output characteristics of n-channel TFTs are influenced by both electron and hole transport properties in the kink regime.

Surface-micromachined, batch-fabricated structures that combine plated-nickel films with polysilicon mechanical flexures to produce individually addressable, magnetically activated devices have been fabricated and tested. Individual microactuator control has been achieved in two ways: 1) by actuating devices using the magnetic field generated by coils integrated around each device and 2) by using electrostatic forces to clamp selected devices to an insulated ground plane while unclamped devices are freely moved through large out-of-plane excursions by an off-chip magnetic field. The present application for these structures is as micromirrors for microphotonic systems where they can be used either for selection from an array of mirrors or else individually for switching among fiber paths. Index Terms - Individually addressed micromirrors, magnetic actuation, surface micromachining, magnetic and electrostatic addressing.

Results of experiments conducted on low frequency noise in quasiself-aligned bipolar n-p-n junction transistors, with widely varying emitter/base junction dimensions, are compared with previous results obtained on devices of the same type. Results show that the power spectral density of base current fluctuations was dependent linearly on the inverse of the area of the emitter/base interface junction. Findings imply the localization of the low frequency noise sources on the interface rather than on the transistor perimeter.

We report on two thermal characterization structures to measure the Seebeck coefficient [Alpha] of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using a commercial 1.2 [[micro]meter] CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for measurement after IC fabrication. The temperature dependent [Alpha] of the two polysilicon layers of the AMS process were measured with both devices. The agreement between the thermoelectric coefficients obtained with the two types of structures is better than 2.1 [[micro]volt] at 300 K.

The performance of low-temperature processed polysilicon thin film transistors is examined. The device is fabricated on polished active polysilicon films. Polishing after annealing is found to significantly enhance performance, while polishing before annealing had no significant influence. Such a touch polish process would be effective in smoothing the surface of the active-layer film, thereby enhancing the poly-Si/SiO2 interface.

Modeling issues in polysilicon emitter bipolar transistors are investigated. Effective values of the minority-carrier diffusion length and mobility are found to be sufficient in describing the minority-carrier injection and storage in the polysilicon region. A general expression for the recombination velocity relative to the poly/mono interface is derived. Minority-carrier injection and storage in the single-crystal region is also investigated.

When surface micromachined devices are combined with on-chip circuitry, any high-temperature processing must be avoided to minimize the effect on active device characteristics. High-temperature stress annealing cannot be applied to these structures. This work studies the effects of deposition parameters and subsequent processing on the mechanical properties of the polysilicon film in the development of a low-strain polysilicon process, without resorting to high-temperature annealing. The films are deposited as a semi-amorphous film and then annealed, in situ at 600 [degrees] C for 1 h, to ensure the desired mechanical characteristics for both doped and undoped samples. This low temperature anneal changes the strain levels in undoped films from -250 to +1100 [Mu][Epsilon]. The best results have been obtained for an 850 [degrees] C anneal for 30 min which is used to activate the dopant (both phosphorus and boron). No further stress annealing was used, and 850 [degrees] C does not present problems in terms of thermal budget for the electrical devices. It is shown that these mechanical characteristics are achieved by forming the grain boundaries during subsequent low temperature annealing, and not during deposition. TEM (transmission electron microscopy) studies have been used to investigate the link between the structure and mechanical strain. This has shown that it is the formation of the grain boundary rather than the grain size which has a significant effect on strain levels, contrary to reports in the literature. Using the above-mentioned deposition process, a series of experiments have been performed to establish the flexibility in subsequent processing available to the designer. Therefore, by careful consideration of the processing, a low-temperature polysilicon process, which can be used to fabricate thin micromachined structures, has been developed. [138]

A study analyzes thin textured tunnel oxide prepared by the thermal oxidation of thin polysilicon film on Si substrate (TOPS). A textured Si/SiO2 interface results from the rapid diffusion of oxygen through the grain boundaries of thin polysilicon film into the Si substrate and the increased oxidation rate at the grain boundaries. This results in localized high fields and increases electron injection into TOPS. Electron conduction efficiency is higher and electron trapping rate lower in TOPS, as compared to the normal tunnel oxide.

A microactuator technology that combines magnetic thin films with polysilicon flexural structures is described. Devices are constructed in a batch-fabrication process that combines electroplating with conventional lithography, materials, and equipment. A microactuator consisting of a 400 x (47 - 40) x 7 [[[micro]meter].sup.3] rectangular plate of NiFe attached to a 400 x (0.9 - 1.4) x 2.25 [[[micro]meter].sup.3] polysilicon cantilever beam has been displaced over 1.2 mm, rotated over 180 [degrees], and actuated with over 0.185 nNm of torque. The microactuator is capable of motion both in and out of the wafer plane and has been operated in a conductive fluid environment. Theoretical expressions for the displacement and torque are developed and compared to experimental results.

A two-dimensional simulation model for dopant diffusion in polysilicon includes dopant clustering inside the grain and on the grain boundary as well as dynamic grain growth. The grain growth depends on the diffusion coefficient of dopants and on the process temperature. The thermal treatment is affected by the trapping/emission processes between grain interiors and boundaries and the grain growth, for high dopant concentration. The model assumes the polysilicon grains to be small squares.

The organic chemistry of silicon is barely a century old but it is now very actively pursued. In particular, there is now great interest in polysilanes bearing functional groups. This article reviews the various synthetic routes that have been developed to achieve particular polymeric configurations and then discusses, in the light of their unique properties, the many potential applications in the electronic field.

The proposed design process of a novel dual poly-Si gate is needed for sub-1/4-micrometer complementary metal oxide semiconductors (CMOS) to adopt surface-channel operation for both nMOS and pMOS. The technology involves a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate deposition of in situ doped n+ and p+ poly-Si for the nMOS and pMOS gates.

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465 [degrees] C. For the Si films annealed at 750 [degrees] C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at [Lambda] = 405 nm), the potential barrier height [[Phi].sub.B] due to the grains, and the field-effect mobility, [[Mu].sub.n,p], of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called 'grains' of the films annealed at 600 [degrees] C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance.

A high-density and high speed SRAM cell is designed and manufactured using an advanced TFT memory cell technology and a phase-shift lithography that allows patterns with spaces less than 0.25 micro m to be made using a conventional stepper. The cell area is very small but the functioning of the cell is stable. A leakage current of 2 fA/cell and an on-/off-current ratio of 4.6 multiplied by 10 to 6th power are obtained with polysilicon PMOS TFT in a memory cell.

The process of pulse current trimming of polysilicon resistors investigated by using a simple technique. The investigation provides a method for the efficient implementation of the pulse current trimming in the manufacture of large scale integrated circuits. The implementation also reveals that the during the manufacture of large scale integrated circuits.

The investigation of the low-frequency noise in polysilicon emitter bipolar transistors reveals that the 1 f noise is caused by the barrier height fluctuations for majority and minority carriers. The investigation is performed on transistors with different geometrics and properties of the oxide layer. The 1 f noise arises from the oxide layer located at the monosilicon polysilicon interface.