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A qualitative model for the programming physics of 90-nm silicided polysilicon fuses is presented. Finding reveals the achievement of an increase in resistance by [10.sup.7] times.

An investigation is described into the effects of an in-situ hydrogen bake and an ex-situ hydrofluoric acid (HF) etch prior to polysilicon deposition on electrical characteristics of bipolar transistors fabricated with low thermal budget in-situ phosphorus-doped polysilicon emitter contacts. Low value of emitter resistance obtained with a high defect density single-crystal silicon emitter suggests applications involving deep submicron Si bipolar or SiGe heterojunction bipolar transistors (HBT) in circumstances where the thermal budget is constrained.

Base-broadening effects caused by extrinsic base implantation in SiGe heterojunction bipolar transistors (HBT) can be suppressed by introducing a buried carbon layer. The carbon layer is introduced under the SiGe/Si base prior to epitaxy.

Quantum-mechanical behaviour of charge carriers at the polysilicon/oxide interface was examined.

A high quality polysilicon oxide that combines N20 nitridation and chemical mechanical polishing processes is described.

A thermal actuator to determine polysilicon fracture strength and fatigue is presented.

Polysilicon gate effects on the random dopant induced threshold voltage fluctuations in MOSFET's are examined.

A high-speed capacitive humidity sensor was integrated on a polysilicon heater.

An experimental and theoretical demonstration of the impact of tunneling currents and channel resistance on the measured gate-to-channel capacitance using long-channel metal oxide semiconductor field effect transistors with sub-20-angstrom gate oxide is presented. A model is derived for the terminal capacitance in terms of tunneling conductance, intrinsic capacitances, measurement frequency and channel length. The model is useful in characterizing a measured extrinsic capacitance fall-off in strong inversion and its relationship with the oxide thickness and channel length of the test structure.

A study was conducted to analyze a lateral type polysilicon field emission triode utilizing standard photolithography and a local oxidation of polysilicon method in a lateral direction. The techniques supported good reproducibility in shaping sharp electrode tips and controlling the short cathode-to-gate inter-electrode distance. Results indicated that the device featured excellent electrical properties.

A study was conducted to analyze the profile and dimension control mechanism in polysilicon gate etching. A two-dimensional etching topography simulator was utilized to carry out the analysis. The reaction times were computed using interactions between incoming ion/radical fluxes. Plasma internal parameters were then modeled as input data of the simulator. In addition, a qualitative guideline was proposed to realize anisotropic etched-profile formation and the dimension difference minimization.

A physical-based analytical current model of polycrystalline silicon thin-film transitors for circuit simulation that is characterized by temperature dependence, barrier potential at grain boundaries and drain induced grain barrier lowering and the kink effect is introduced. This model includes an accurate model of the kink effect whose parameters can be used in polysilicon thin film transistors with different sizes.

The transient current measurement of polysilicon thin film transistors is examined with particular focus on the presence of an 'overshoot' in the transient response. There is 'capacitance overshoot' when the gate-source capacitance CGS can be greater than the oxide capacitance C(sub OX)WL at low frequency and high voltage. A method for quantifying the transient response is introduced and the impact of the capacitance overshoot is illustrated. The results are discussed.

In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 [[micro]meter] 64 x 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell.

A chemical vapor deposition tetra-ethyl-ortho-silicate oxide which is deposited on the phosphorus in-situ/POCl3 doped polysilicon and applied with N2O rapid thermal annealing is found to have desirable characteristics. These include asymmetric J-E features and a very large charge-to-breakdown of up to 110 C/Cm(super 2) because of the good polysilicon/oxide interface morphology derived by the replacement of POCl3 doping with in-situ doping and the rapid thermal annealing in N2O.

MOSFET dosimeters incorporating an electrically floating polysilicon gate have been fabricated in a commercial CMOS technology. Charge is placed on the floating gate by tunnelling from a small overlapping injector gate. Subsequent irradiation partially discharges the floating gate, producing a change in threshold voltage which can be used to infer the absorbed dose. No external power source is required during this sensing period. Sensitivities up to 70 [mVGy.sup.-1] (0.7 mV/rad) have been obtained for temperature-compensated matched-pair dosimeters under 60Co gamma irradiation.

Research has established a low field leakage current model which describes low-temperature laser recrystallized polysilicon thin-film transistors. The model is applicable at low drain to source voltage and accounts for active layer length, bias-stress, density-of-states and the effects of leakage current on device active layer thickness. Two-dimensional simulation techniques are discussed.

Research was conducted to examine floating body effects in polycrystalline silicon thin film transistors (TFT) using numerical simulations. Two dimensional simulations were utilized to analyze the kink effect in poly-TFTs which allowed a precise description of the microscopic phenomena occurring in the device. Results indicated that the output characteristics of n-channel TFTs are influenced by both electron and hole transport properties in the kink regime.

We report on two thermal characterization structures to measure the Seebeck coefficient [Alpha] of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using a commercial 1.2 [[micro]meter] CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for measurement after IC fabrication. The temperature dependent [Alpha] of the two polysilicon layers of the AMS process were measured with both devices. The agreement between the thermoelectric coefficients obtained with the two types of structures is better than 2.1 [[micro]volt] at 300 K.

The performance of low-temperature processed polysilicon thin film transistors is examined. The device is fabricated on polished active polysilicon films. Polishing after annealing is found to significantly enhance performance, while polishing before annealing had no significant influence. Such a touch polish process would be effective in smoothing the surface of the active-layer film, thereby enhancing the poly-Si/SiO2 interface.

Modeling issues in polysilicon emitter bipolar transistors are investigated. Effective values of the minority-carrier diffusion length and mobility are found to be sufficient in describing the minority-carrier injection and storage in the polysilicon region. A general expression for the recombination velocity relative to the poly/mono interface is derived. Minority-carrier injection and storage in the single-crystal region is also investigated.

A study analyzes thin textured tunnel oxide prepared by the thermal oxidation of thin polysilicon film on Si substrate (TOPS). A textured Si/SiO2 interface results from the rapid diffusion of oxygen through the grain boundaries of thin polysilicon film into the Si substrate and the increased oxidation rate at the grain boundaries. This results in localized high fields and increases electron injection into TOPS. Electron conduction efficiency is higher and electron trapping rate lower in TOPS, as compared to the normal tunnel oxide.

A two-dimensional simulation model for dopant diffusion in polysilicon includes dopant clustering inside the grain and on the grain boundary as well as dynamic grain growth. The grain growth depends on the diffusion coefficient of dopants and on the process temperature. The thermal treatment is affected by the trapping/emission processes between grain interiors and boundaries and the grain growth, for high dopant concentration. The model assumes the polysilicon grains to be small squares.

The proposed design process of a novel dual poly-Si gate is needed for sub-1/4-micrometer complementary metal oxide semiconductors (CMOS) to adopt surface-channel operation for both nMOS and pMOS. The technology involves a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate deposition of in situ doped n+ and p+ poly-Si for the nMOS and pMOS gates.

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465 [degrees] C. For the Si films annealed at 750 [degrees] C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at [Lambda] = 405 nm), the potential barrier height [[Phi].sub.B] due to the grains, and the field-effect mobility, [[Mu].sub.n,p], of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called 'grains' of the films annealed at 600 [degrees] C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance.

A high-density and high speed SRAM cell is designed and manufactured using an advanced TFT memory cell technology and a phase-shift lithography that allows patterns with spaces less than 0.25 micro m to be made using a conventional stepper. The cell area is very small but the functioning of the cell is stable. A leakage current of 2 fA/cell and an on-/off-current ratio of 4.6 multiplied by 10 to 6th power are obtained with polysilicon PMOS TFT in a memory cell.

The process of pulse current trimming of polysilicon resistors investigated by using a simple technique. The investigation provides a method for the efficient implementation of the pulse current trimming in the manufacture of large scale integrated circuits. The implementation also reveals that the during the manufacture of large scale integrated circuits.

The investigation of the low-frequency noise in polysilicon emitter bipolar transistors reveals that the 1 f noise is caused by the barrier height fluctuations for majority and minority carriers. The investigation is performed on transistors with different geometrics and properties of the oxide layer. The 1 f noise arises from the oxide layer located at the monosilicon polysilicon interface.

The hetero-emitter-type characteristics of phosphorus doped poly-Si emitter transistor is caused by the presence of potential barriers on the valence band and conduction band at the interfaces. The phosphorus doped poly-Si emitter is formed by the crystallized ion from an in situ phosphorus doped amorphous Si-films. The barriers are formed primarily due to the band discontinuity existing at the interface.

X-ray diffraction measurements on the hetero-emitter-type characteristics of bipolar transistors reveal the existence of a large lattice deformation at the interface which consists of Si substrates and poly-Si layers. The lattice deformation provides a tensile stress of 1 giga pascals to the bipolar transistors.

The investigation of the characteristics of a very-high-speed silicon bipolar transistor having ultra-shallow junctions reveals that these transistors exhibit an ideal current-voltage characteristics. The investigation is performed by the process of thermal diffusion. The transistors are fabricated by the double-polysilicon self-aligned bipolar technology. The investigation also reveals that the transistors exhibit low emitter resistance and large current gain.

Remote plasma chemical vapor deposition (CVD) and plasma hydrogenation techniques help fabricate polycrystalline silicon thin film transistors (poly-Si TFTs) at low temperatures. Pulsed laser annealing crystallizes the hydrogenated amorphous silicon films and yields a crystal grain size of less than 100 mm to the power of 17 per cubic cm. The poly-Si TFTs constructed by plasma hydrogenation, laser crystallization and CVD have a p- and n-channel carrier mobility of 400 sq cm Vs and 640 sq cm Vs and threshold voltages of -1.5 V and 0.8 V, respectively.

Comparison of the influence of three types of plasma etching chemistries for nitride post-processing and patterning on the electrical contact resistance and mechanical adhesion between two polysilicon layer structures reveals that all three chemistries generate good mechanical adhesion and that the CHF3 CF4- and CF4 SF6-based chemistries yield good electrical contact. The CHF3 N2-based chemistry induces a polymer film between the polysilicon layers that causes electrical insulation. CHF3 N2-based chemistry offers high-selectivity while the CHF3 CF4-based chemistry offers low-selectivity.f

Examination of the increase in sheet resistance in TiSi2-polysilicon films reveals that it occurs during the narrowing of the line width, with three different regions defining the correlation between sheet resistance and line width. Large inter-grain layers with low silicide levels cause the increase in sheet resistance. NiSi films, unlike TiSi2 films, do not display an increase in sheet resistance.

High current pulses in the ion-beam-sputtered polysilicon resistors help the electrical trimming process in the resistors. The pulses induce Joules heating effects, resulting in the passivation of the interfacial grain boundaries at low and high currents. The trimming process does not affect the components of the monolithic chip and is simulated using small-signal resistivity and large-bias conduction models.

Advanced polysilicon emitter bipolar transistors are studied using the parameter extraction method. Equivalent circuit parameter predetermination by the use of analytical expressions of de-embedded Z parameters of the devices forms the basis for this method. Optimization of the parameter extraction process requires the parameters as initial values. The test structures extract the interconnection circuit parameters which have the radio frequency probe.

Studies on polysilicon depletion effect on I-V properties for various MOSFETs reveal that a decrease in oxide thickness (tox), polysilicon gate concentration (NP) or increase in substrate impurity concentrations (ND) causes substantial I-V characteristic degradation. An analysis of a modified Pao-Sah model that includes polysilicon depletion factor reveals that model results agree well with experimental data for all device operation domains. The model calculates device I-V characteristics as a function of tox, NP and ND.

Studies on polysilicon thin film transistor (TFTs) characteristics reveal that H2-O2-plasma treatment to polysilicon TFTs improves TFT performance more than H2-plasma or O2-plasma treatment alone. H2-plasma-treated TFTs reveal saturation characteristics whereas O2-plasma-treated TFTs do not. Field effect conductance method tests reveal that H2-O2-plasma treatment reduces device trap state density.

The total dose radiation response of two classes of floating gate nonvolatile memory devices is examined. While the hardness of commonly studied double polysilicon cells is restricted to a few kilorads, devices having only one polysilicon layer are shown to be much more radiation-hard. This is mainly due to the thinner oxide that can be used in the coupling capacitor of such cells. It is also shown that the contribution of the field oxide regions, present under the floating gate of the cells, is of major importance for their radiation response. Finally, the programming behavior of the devices is shown to remain fairly unaffected by the ionizing radiation.

A fabricated stacked-amorphous silicon (SAS) film provides a shallow junction diode with enhanced performance capabilities. A small reverse leakage current was released by the SAS emitter, and resulted from a diffusion current. The periphery generation current was not a significant contributor to the total leakage. A temperature as low as 600 degrees Celsius has been registered as the processing temperature for the fabricated SAS emitter.

Polysilicon buffered LOCOS (PBL) has been widely utilized for advanced isolation applications as moderately low lateral oxide encroachment may be achieved without defect formation. Unfortunately, PBL does not exhibit sufficient field oxide recess to support aggressive device scaling without introduction of processes which are difficult to control. Recently, polysilicon encapsulated local oxidation (PELOX) has been proposed as an easily scaled isolation technique that exhibits LOCOS equivalent recess. The integration of PELOX into an existing PBL 1 Mb DRAM baseline process is described. PELOX integrated PBL (PIPBL) is demonstrated to enhance final field oxide recess without increasing encroachment. The improved final field oxide recess is shown to provide increased process margin as evidenced by superior probe yield.

A proposed method for obtaining high-speed phosphorus direct doping into thin polysilicon on glass substrate using a bucket-type high-density ion source and without mass separation is presented. Results show that low sheet resistance can be obtained through short-time doping into a very thin layer. Low-temperature polysilicon thin-film transistors (TFTs) exhibited similar characteristics as those of TFTs produced through longer doping times.

An experiment to quantify the properties of n+-p-n+ polysilicon loads used to minimize the size of static random access memory cells is presented. It describes the dependence of the polysilicon load resistance on the fixed positive charges and gate oxide thickness of a related thin film transistor. This dependence results in a drop of the polysilicon loadresistance after exporsure to post-metallization anneal at low temperatures.

A hole transport equation is obtained to describe the effect of oxide breakup on the base current of n+-polysilicon emitter bipolar devices. Based on a transport model of the emitter's polysilicon/silicon interface, the equation accounts for the observed base current variances as a function of a percentage of the interface void. It also forecasts a lower reliance of the base current on the percentage of interface oxide breakup area for devices satisfying certain conditions.

A review of the theories concerning polysilicon emitter bipolar transistors is conducted to clarify the ambiguity surrounding current gain enhancement in the device. It covers the various fabrication procedures currently in use and their effect on the phenomena and develops a single model for describing the base current in the transistor. Experimental data on such transistors are also re-evaluated in light of the unified model to identify the physical mechanisms responsible for the phenomena under different fabrication processes.

The interdependence between oxide breakup and other characteristics of the polysilicon-emitter bipolar transistors is quantified via the insertion of kinetic terms in the bipolar carrier transport equations. The study investigated performance of such devices as a function of process conditions. Results show heavy reliance of the emitter resistance on the interfacial oxide continuity. Proof of the interfacial oxide's and polysilicon layer's role in improving the gain of the device is also shown.

Research into the performance of large-grain polysilicon-on-insulator metal oxide semiconductor transistors is presented. The study shows that they perform in gigahertz range, reaching 3.4 GHz and 2.6 GHz at 1.2 micronm channel length.

Reverse short channel effect modulation by poly-Si doping level is proposed in the context of oxide thickness changes.

A study of the mechanical and physical characteristics of a new single-Si poly-Si direct bonding (SPSDB)-based dielectric isolated (DI) wafer helps modify the wafer size, wafer warpage and device patterning size appropriately. The SPSDB-based DI wafers with 5-inch size have a high bonding strength and constant warpage height. The bonding strength of the DI wafers bonded at 1100 degrees Celsius are similar to that of the thermal oxidizing layer interface.