Experimental characterization of the diode-type polysilicon loads for CMOS SRAM

An experiment to quantify the properties of n+-p-n+ polysilicon loads used to minimize the size of static random access memory cells is presented. It describes the dependence of the polysilicon load resistance on the fixed positive charges and gate oxide thickness of a related thin film transistor. This dependence results in a drop of the polysilicon loadresistance after exporsure to post-metallization anneal at low temperatures.