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Titanium-based contacts are envisioned for the integration of III–V device contacts on a 300-mm platform, such as photodetectors, semiconductor optical amplifiers (SOAs), and III–V silicon hybrid lasers. For the first time, the impact of the thermal budgets of process integration, back-end of line (BEOL), and long-term thermal stress on the electrical characteristics of the Ti/p-In0.53Ga0.47As and Ti/n-InP contacts has been investigated. Additional physical characterizations have been used to supplement the electrical properties on both systems. Results have indicated that, given a thermal budget between 350 °C and 450 °C during 60 s right after metal deposition, 1) Ti as a contact metal has led to contact resistivity in low $10^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ for p-contacts and in mid $10^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ for n-contacts, which is in accordance with the device requirements; and 2) process integration, BEOL, and long-term thermal stress will not induce any change of the electrical properties. In the scope of III–V silicon hybrid laser contact integration, Ti has hence been evidenced as a suitable candidate for both p- and n-contacts.

In this paper, we present the hybrid III–V/Si photonic platform developed in CEA-LETI. The overall integration is done in a fully CMOS compatible 200-mm technology, scalable to 300-mm wafers, leveraging the large-scale integration capabilities of silicon photonics. III–V material is integrated on top of a mature silicon photonic front-end wafer through direct molecular bonding enabling the monolithic integration of light sources. DFB and distributed Bragg reflector (DBR) laser reference designs are used as test vehicles for the process validation. A modular approach is used in order to minimize the impact on the already qualified silicon-based devices. Collective III–V die bonding is proposed in this platform. CMOS compatible metallizations are used to form ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². A planarized two-metal-level BEOL is used to connect the device, leading to a drastic reduction of series resistance. Finally, the functionality of both types of lasers is demonstrated with SMSR up to 50 dB and maximum output power of 5 mW.

International audience; Although silicide oxidation was studied 20years ago, the interest in obtaining a robust process for new applications remains significant today. Indeed, the new architectural development process requires dense and narrow spaces. In this study, attempts were made to bury a silicide layer under a protective silica layer in order to keep the physical and electrical properties of the silicide constant after oxidation. Thus, we first tried to reproduce and study these conditions and, once acquired, aimed to decrease the oxidation temperature in order to meet industrial requirements. Titanium (Ti) and nickel (Ni) were chosen for their metallurgical interest and their integration capability in devices. Four different groups of silicide (TiSi, TiSi2, Ni2Si, NiSi) were targeted by adjusting the temperature. Then, all of the silicides, including one pure Si wafer, were oxidized using dry, wet and plasma techniques. In situ scanning electron microscopy, spectroscopic ellipsometry and X-ray reflectivity measurements were carried out simultaneously before and after oxidation of the silicide to characterize the SiO2 and silicide morphology, thickness and density. We found that after 800 degrees C dry oxidation, Ti silicide was totally oxidized, which was an unexpected result. But, Ni silicide showed an agglomeration phenomenon after 500 degrees C and 800 degrees C dry oxidation. Although, after wet oxidation, it was confirmed that the highest SiO2 thickness formed, the NiSi surface roughness was higher. In the case of plasma oxidation, we obtained a thin layer (approximate to 1nm) of SiO2 on NiSi with an extremely smooth surface.

Thin films of superconducting V$_3$Si were prepared by means of RF sputtering from a compound V$_3$Si target at room temperature onto sapphire and oxide-coated silicon wafers, followed by rapid thermal processing under secondary vacuum. The superconducting properties of the films thus produced are found to improve with annealing temperature, which is ascribed to a reduction of defects in the polycrystalline layer. Critical temperatures ($T_\text{c}$) up to $15.3\,$K were demonstrated after thermal processing, compared to less than $1\,$K after deposition. The $T_\text{c}$ was found to always be lower on the silicon wafers, by on average $1.9(3)\,$K for the annealed samples. This difference, as well as a broadening of the superconducting transitions, is nearly independent of the annealing conditions. In-situ XRD measurements reveal that the silicide layer becomes strained upon heating due to a mismatch between the thermal expansion of the substrate and that of V$_3$Si. Taking into account the volume reduction due to crystallization, this mismatch is initially larger on sapphire, though stress relaxation allows the silicide layer to be in a relatively unstrained state after cooling. On oxidized silicon however, no clear evidence of relaxation upon cooling is observed, and the V$_3$Si ends up with an out-of-plane strain of 0.3\% at room temperature. This strain increases as the sample is cooled down to cryogenic temperatures, though the deformation of the polycrystalline layer is expected to be highly inhomogeneous. Taking into account also the reported occurrence of a Martensitic transition just above the critical temperature, this extrapolated strain distribution is found to closely match an existing model of the strain dependence of A-15 superconducting compounds., 7 pages, 5 figures

In this work, we report on the material properties of superconducting heavily boron-doped polycrystalline Silicon-On-Insulator (SOI) thin layers fabricated by pulsed laser induced recrystallization under experimental conditions compatible with high volume CMOS integration. This approach combines boron implantation and ultra-violet nanosecond laser annealing (UV-NLA) to reach maximum dopant activation by exceeding boron solid solubility in silicon. For our process conditions, material characterizations revealed five laser annealing regimes, including the SOI full-melt, which leads to the formation of superconducting polycrystalline layers. The average critical temperature was found to be around 170 mK, neither influenced by energy density nor the number of laser pulses. In addition, thanks to low temperature measurements coupled with magnetic field variations, we highlighted a type II superconductor behavior due to strong impurity effect. The deducted average effective coherence length of hole pairs in our layers was estimated around 85 nm.

Nickel-based metallization are envisioned for the p-contact integration of III-V / silicon hybrid lasers on a 300 mm platform. The electrical and physical characteristics of Ni 0.9 Pt 0.1 and Ni thin films on In 0.53 Ga 0.47 As layers have been studied. For the first time, the impact of the thermal budget of the process integration and laser operations on the contact integrity have been investigated. Results have shown that in the case of the Ni 0.9 Pt 0.1 / p-In 0.53 Ga 0.47 As system, with a rapid thermal annealing between 350 and 450 °C for 60 s applied after metal deposition, promising contact resistivities have been extracted (low 10–5 - high 10–6 Ω.cm2) along with a good electrical stability after process integration and laser operations. The Ni / p-In 0.53 Ga 0.47 As system have exhibited lower contact resistivities (low 10–6 - high 10–7 Ω.cm2) granted a rapid thermal annealing between 400 and 500 °C after metal deposition. A strong electrical stability after integration steps and laser operations has also been evidenced. Results suggest that the Ni / p-In 0.53 Ga 0.47 As system constitutes the most promising option for p-contact integration.

The development of Complementary Metal Oxide Semiconductor (CMOS)-compatible contact technology on III–V materials based on Ti for electronics or photonics applications was studied. In this framework, solid-state reactions between Ti thin films (20 nm) and In0.53Ga0.47As layers grown on InP substrates were studied from the as-deposited state up to 550 °C using a combination of advanced X-ray diffraction (in-plane reciprocal space mapping), Auger electron spectroscopy and transmission electron microscopy analyses. The phase formation sequence was solved. At low temperature, an amorphous Ti–Ga–As intermixing layer coexists with the Ti film. As of 250 °C, the first crystalline phase to form is Ti 2 Ga 3 . At 300 °C, a new crystalline phase appears, namely TiAs 2 . On the other hand, TiAs and metallic In form at 350 °C and Ti is completely consumed between 450 and 500 °C. The diffusion of the various species lead to the formation of a non-nominal Ga-rich In x Ga 1−x As layer and at 550 °C to the formation of polycrystalline GaAs. Ti was found to be the main diffusing species at low temperature whereas III and V elements are the dominant diffusing species at higher temperatures. The nature of the phases formed above and below the original Ti/InGaAs interface might explain the In accumulation at the interface, the TiAs phase acting as a diffusion barrier.

We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.

International audience; Using a metal-organic tungsten based precursor, a fluorine-free tungsten thin film has been obtained. The process deposition recipe includes a plasma-enhanced CVD (PECVD) step and atomic layer deposition (ALD) cycles. A set of physicochemical characterizations including X-ray reflectivity (XRR), in-plane X-ray diffraction (XRD), wavelength dispersive X-ray fluorescence (WDXRF), plasma profiling time of flight mass spectrometry (PPTOFMS) and microscope observations has been realized in order to study the W thin film structure and properties. The film is perfectly conformal whatever the structure size investigated (from tens of nanometers to micrometers wide). It was also highlighted that the F-free W film exhibits the lowest electrical resistivity phase (α-W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located at the W film / substrate interface is present. This interface layer (IL) contains impurities, including carbon and oxygen, due to ligand decomposition. This IL might be deposited during the soak step or during the PECVD step. The W liner with thicknesses ranging from 3 to 4 nm has been implemented on PCRAM structures in order to evaluate its impact on contact plug resistivity. First electrical results are promising and demonstrate the interest of using a F-free low resistance W liner. At the aspect ratio studied, the gain in terms of contact plug resistivity is about 20% compared to the process of reference using a TiN liner. Modeling shows that this benefit is mainly due to the reduction of interface resistances.

In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metallizations have been investigated for the purpose of forming low resistivity and Si CMOS-compatible contacts to n-InP. The innovative Ni2P metallization combined with an in situ Ar+ preclean represents the most suitable available solution for the formation of ohmic contacts with a specific contact resistivity as low as $4.3 \times 10^{-6}~\Omega ^{2}$ on such a semiconductor. The latter additionally presents the advantage of being stable at least up to 350 °C and could therefore withstand additional integration processes conducted at this temperature.

3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits on device density and performance are achieved. However, although the thermal processing of top transistors is currently restricted in order to avoid bottom CMOS degradation, it has been highlighted that Ni0.80Pt0.10 silicide source/drain (S&D) contact remains the most sensitive element to the thermal budget, especially on raised Si0.7Ge0.3:B S&D for pMOS transistors. In this context, a complete and systematic study on self-aligned silicide (SALICIDE) process has been proposed: alternative metallization as well as source and drain surface pre-treatments have been carried out. Indeed, a novel Ni-based silicide, the Ni0.9Co0.1 provides a better stability on unpatterned 300 mm wafers. This stability has been further improved when combined with epitaxial silicon capping layer (Si-Cap) and Si0.7Ge0.3:B S&D pre-amorphization implant (PAI) using Ge beam. For the first time, a successful Ni0.9Co0.1 SALICIDE implementation has been demonstrated on pMOS planar FDSOI transistor with both PAI and Si-Cap. Moreover, the presence of Si-Cap contributes to reduce silicide roughness and limits Ge partition that damage Si0.7Ge0.3:B S&D. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Silicon photonics has generated an amazing interest for many years to address the challenges of numerous applications including optical communications, sensing, and quantum information to name few. A review of the main building blocks to emit, guide, modulate, and detect light on silicon chip is described and a special focus is given on the large possibilities offered by the hybrid integration on silicon photonics platform for the development of reliable and efficient on-chip functionalities.

In this progress review, an overview of the CMOS-compatible contact technology developed at the CEA-Leti for Si photonics applications is proposed. The elaboration of III–V/Si hybrid lasers implies the development of ohmic contacts on n-InP and p-InGaAs III–V materials. In this way, a contact technology fully compatible with a Si-Fab line was developed. The results presented in this manuscript cover a wide scope: from surface preparation and solid-state reaction to electrical results and integration guidelines. The metallurgy of several systems including Ni/InGaAs, Ni/InP, Ti/InGaAs and Ti/InP was studied. The direct metallization of III–V materials using Ni2P was also introduced. Most of the studied metallizations provided efficient solutions for achieving ohmic contacts on n-InP and p-InGaAs. Finally, the contact technology developed in the framework of this study was successfully integrated on 200 mm CMOS-compatible III–V/Si hybrid lasers.

This study focuses on silicide formation on phosphorus in-situ doped samples, the phosphorus diffusion and its distribution during the solid-state reaction. The silicidation is achieved with a 16 nm thin film of Ni0.9Pt0.1 followed by a two steps annealing process using rapid thermal annealing, selective etching and dynamic surface annealing. Silicide formation is investigated thanks to in-situ X-ray diffraction and X-ray reflectivity, while the phosphorus concentration profiles after silicidation are obtained by Time-of-Flight Secondary Ion Mass Spectroscopy. Based on these profiles, simulation of the phosphorus redistribution is achieved. The latter is linked to a fast diffusion in the silicide and at its grain boundaries. This feature is put forward to explain how doping may influence the phase sequence of silicide formation.

In this work, the solid-state reaction between a 7 nm thick Ni0.9Co0.1 film and a silicon substrate has been studied. By combining various characterization methods (e.g. sheet resistance measurement, X-ray reflectivity, X-ray diffraction), a comprehensive phase sequence of the NiCo silicide formation has been proposed. At low temperature, we observed the formation of metal-rich Ni2Si-like phases: δ-(NiCo)2Si and θ-(NiCo)2Si. Contrary to Ni0.9Pt0.1 based silicides, the δ-Ni2Si phase appears before the θ-Ni2Si one. Beyond 320 °C, the (NiCo)Si monosilicide formation is initiated and this latter is complete at 400 °C. The presence of Co strongly decreases the NiSi2 formation temperature. This early formation of disilicide allows avoiding film agglomeration and enhances the thermal stability of NiSi silicide. Complementary studies using wavelength dispersive X-ray fluorescence allowed studying the cobalt behavior and highlighted the formation of a Co composition gradient into the metal-rich silicide phases at relatively low temperature (220–260 °C).

From surface preparation and solid-state reaction to laser integration, a short overview of the CMOS-compatible contacts developed in our group on n-InP and p-InGaAs for Si photonic applications is proposed.

Silicon photonic platforms are becoming more and more mature with competitive devices suitable for increasing needs of HPC (High Performance Computing) systems and datacenters. Compared to bulk III-V technologies, Si photonic technologies are suffering from the lack of integrated light source. Several works have been done in the past years to integrate laser on silicon using III-V direct bonding on top of patterned silicon. These demonstrations were using a CMOS compatible process for the silicon part but all the process steps following the introduction of the III-V material were done with small wafer diameter III-V fabrication lines. With such integrations, the cost advantage of silicon photonics based on the use of CMOS platforms and large wafer format is no more valid. In this paper we present the integration of a hybrid III-V/Si laser using a fully CMOS compatible 200mm technology. The laser is integrated in a mature photonic platform. The additional process modules required for this integration will be deeply described. These modules are localized silicon thickening using damascene process, Bragg reflector patterning with DUV lithography, III-V patterning and ohmic contact formation with no lift-off and without noble metal. This integration is compatible with a multi metal levels planar BEOL, mandatory for photonic circuit design. The first DFB lasers fabricated with this new platform are operating at 1310nm with a threshold current around 60mA, a SMSR larger than 45dB and more than 1.5mW optical power in the output waveguide. New laser designs, specifically adapted for this new process, will be introduced and fabricated.

In this paper, we present a short overview of the CMOS-compatible contact technology developed in our group on n-InP and p-InGaAs for Si photonic applications. Obtained results cover a wide spectrum: from surface preparation and solid-state reaction to electrical results and laser integration. The metallurgy of several systems including Ni / InGaAs, Ni / InP, Ti / InGaAs and Ti / InP has been studied. Most of the metallizations studied provide efficient solutions for contacting n-InP and p-InGaAs. Finally, guidelines for integrating low resistivity contacts are proposed.

Phosphorus diffusion and its distribution during the solid-state reactions between Ni0.9Pt0.1 and implanted Si substrates are studied. Silicidation is achieved through a first rapid thermal annealing followed by a selective etching and a direct surface annealing. The redistribution of phosphorus in silicide layers is investigated after the first annealing for different temperatures and after the second annealing. Phosphorus concentration profiles obtained thanks to time of flight secondary ion mass spectrometry and atom probe tomography characterizations for partial and total reactions of the deposited 7 nm thick Ni0.9Pt0.1 film are presented. Phosphorus segregation is observed at the Ni0.9Pt0.1 surface and at Ni2Si interfaces during Ni2Si formation and at the NiSi surface and the NiSi/Si interface after NiSi formation. The phosphorus is evidenced in low concentrations in the Ni2Si and NiSi layers. Once NiSi is formed, a bump in the phosphorus concentration is highlighted in the NiSi layer before the NiSi/Si interface. Based on these profiles, a model for the phosphorus redistribution is proposed to match this bump to the former Ni2Si/Si interface. It also aims to bind the phosphorus segregation and its low concentration in different silicides to a low solubility of phosphorus in Ni2Si and in NiSi and a fast diffusion of phosphorus at their grain boundaries. This model is also substantiated by a simulation using a finite difference method in one dimension.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

In this paper we demonstrate the first integration of a hybrid III-V/Si laser in a fully CMOS compatible 200mm technology. Device with SMSR up to 50 dB and a maximum output power of 4mW coupled in the waveguide have been measured. The fabrication flow is fully planar and compatible with large scale integration silicon photonics circuit.

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

International audience; The metallurgical properties of the Ti/InP system meet a great interest for its use as a contact in the scope of various applications such as the Si Photonics. The investigations conducted on this system highlight the initiation of a reaction between the Ti and the InP substrate during the deposition process conducted at 100 °C. The simultaneous formation of two binary phases, namely, Ti$_2$In$_5$ and TiP, is attributed to the compositional gradient induced in the InP by the wet surface preparation and enhanced by the subsequent $in situ$ Ar$^+$ preclean. Once formed, the TiP layer acts as a diffusion barrier inhibiting further reaction up to 450 °C in spite of the presence of an important Ti reservoir. At higher temperature, however, i.e., from 550 °C, the reaction is enabled either by the enhancement of the species diffusion through the TiP layer or by its agglomeration. This reaction gives rise to the total consumption of the Ti$_2$In$_5$ and Ti while the TiP and In phases are promoted.

International audience; In this paper, in order to provide a comprehensive overview of the opportunities and limitations of the metal/insulator/semiconductor contacts approach, expected performance based on ideal contact simulations as well as key practical aspects are presented. While the former give us a glimpse of the theoretical potential of this paradigm, mainly to contact nFETs, the latter highlights concerns about the electrical characterization of such contacts along with issues occurring during their physical implementation. (c) 2017 The Japan Society of Applied Physics

International audience; Solid-state reactions between Ni1-uPtu (0< u < 0.15 at.%) and Si0.7Ge0.3 after rapid thermal annealing at 280 to 700 degrees C were studied. Numerous physical and chemical characterizations such as sheet resistance analysis, scanning electron microscopy, transmission electron microscopy, Xray diffraction measurement, and atom probe tomography were used to determine the formation and morphological degradation mechanisms of the pure Ni-based germanosilicide. In particular, atom probe tomography was used to quantitatively determine the element distribution in 3D and at the atomic scale. Similar mechanisms for the degradation were found for the Ni mono germanosilicide with and without Pt and led to Ge rich Si1-xGex regions that are etched away by the selective etch. These mechanisms, Ge out-diffusion and agglomeration, have a combined effect on the germanosilicide degradation and occurs through Ge and Ni diffusion, respectively. Adding Pt increases the thermal stability of the layer owing to changes in the phase sequence and texture and strong binding with Ge atoms. Several models are developed to explain the different steps of the film morphological degradation. The thermodynamics description of the equilibrium in the quaternary Ni-Pt-Si-Ge system allows us to rule out a pure thermodynamics explanation for the morphological stabilization due to Pt addition. Published by AIP Publishing.

The integration of III-V/Si hybrid lasers on a 300 mm platform for photonic applications requires the development of dedicated CMOS-compatible contacts, for which nickel-based ones are very good candidates. In this scope, this work presents and compares the impact of in situ preclean based on argon (Ar) or helium (He) plasma on the surface integrity of InP prior to the nickel (Ni) contact deposition. The resulting surface morphology, element distribution, phase formation sequence of the Ni/InP system, and electrical behavior of Ni/n-InP contacts are detailed using morphological, structural, and electrical characterizations. The results show that Ar preclean significantly damages the InP surface by generating high roughness and creating indium (In) dots on the top surface, while He preclean seems to induce lighter damages and no In dots. Although the phase sequence of the Ni/InP system is overall the same for each preclean, the electrical behavior differs depending on the nature of the preclean. On one hand, Ni/n-InP Ar-precleaned contacts exhibit nonohmic behavior for each investigated thermal budget. On the other hand, He-precleaned contacts features ohmic behavior for the as-deposited state and thermal anneals up to 350 ° C for 60 s. They, however, become nonohmic after anneals of 400 and 450 ° C for 60 s. These results, hence, suggest that the difference of electrical behavior obtained between Ar and He-precleaned Ni/n-InP contacts is due to differences in the state surface and morphology.The integration of III-V/Si hybrid lasers on a 300 mm platform for photonic applications requires the development of dedicated CMOS-compatible contacts, for which nickel-based ones are very good candidates. In this scope, this work presents and compares the impact of in situ preclean based on argon (Ar) or helium (He) plasma on the surface integrity of InP prior to the nickel (Ni) contact deposition. The resulting surface morphology, element distribution, phase formation sequence of the Ni/InP system, and electrical behavior of Ni/n-InP contacts are detailed using morphological, structural, and electrical characterizations. The results show that Ar preclean significantly damages the InP surface by generating high roughness and creating indium (In) dots on the top surface, while He preclean seems to induce lighter damages and no In dots. Although the phase sequence of the Ni/InP system is overall the same for each preclean, the electrical behavior differs depending on the nature of the preclean. On one han...

Strained SiGe and SiC sources and drains are planned to be used in sub-28nm FDSOI devices in order to improve the carriers mobility. Consequently, silicide-induced relaxation of strained epitaxial layers is a key issue to address in order to fully benefit from the desired effects of strain engineering techniques. This paper deal with the impact of the silicidation process conditions on the strain of Si1-xGex:B layers (x=0.3 and 0.45) and SiC:P with [C]≤1,5%. We show that the strain of epitaxial layers is not affected by the silicidation in the case of Si0.7Ge0.3 and SiC, while a strong degradation of strain occurs with Si0.55Ge0.45. The strain evolution in the channel of a device at various stages of the silicidation process has been followed using dark field electron holography. We show that process parameters can be tuned in order to minimize the reduction of strain induced by the silicidation

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible

To improve 20nm FD-SOI pMOS transistor performances, salicide process must be optimized on SiGe source&drain. In this paper, we propose an investigation on Ni and Pt/Si1-xGex (x=0.15, 0.3) systems. In a first part, process window is studied to determine thermal budget domain where the less resistive phase is stable morphologically and thermically. Solid state reactions in terms of phase sequence, thermal stability and morphology have been examined. At high temperature, two kinds of degradations have been observed. In Ni case, Ge out diffusion leads to the film agglomeration. In Pt case, grain coalescence degrades germanosilicide film. In a second part, contact resistivity has been extracted on lateral germanosilicides thanks to new designed structures. After a validation on Pt/Si system, RC extraction has been carried out on Si1-xGex substrate up to 30% of Ge. RC seems to be better with Pt compared to Ni with the same conditions of process optimizations.

International audience; The solid-state reaction between Ni and In In$_{0.53}$Ga$_{0.47}$As on an InP substrate was studied by X-ray diffraction (XRD) and scanning transmission electron microscopy-energy-dispersive X-ray spec-troscopy techniques. Due to the monocrystalline structural aspect of the so-formed intermetallic, it was necessary to measure by XRD a full 3D reciprocal space mapping in order to have a complete overlook over the crystalline structure and texture of the intermetallic. The formation of the inter-metallic was studied upon several different Rapid Thermal Annealings on the as-deposited samples. Pole figures analysis shows that the intermetallic features a hexagonal structure (P6$_3$$/mmc$) with an NiAs-type (B8) structure. Although only one hexagonal structure is highlighted, the intermetallic exhibits two different domains characterized by different azimuthal orientations, axiotaxial relationship, and lattice parameters. The intermetallic phases seem to present a rather wide range of stoichiometry according to annealing temperature. The texture, structure, and stoichiometry of the intermetallic are discussed along with the evolution of lattice parameters of the Ni-InGaAs phase.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

International audience; The composition and morphology of the product phase after the reaction of Ni thin film with In0.53Ga0.47As substrate at 350 degrees C were investigated by atom probe tomography, X-ray diffraction, and scanning electron microscopy. Results show the formation of a unique Ni-3(In0.53Ga0.47) As phase with a low concentration in-depth gradient of Ni and the decoration of the grain boundaries by In atoms. These analyses indicate that Ni is the main diffusing specie during the growth of Ni-3(In0.53Ga0.47) As phase. The volume of the product phase is higher than the volume of the consumed Ni film as expected for the formation of Ni-3(In0.53Ga0.47) As phase. Published by AIP Publishing.

International audience; Opening the way to large bandwidths and high data rates Silicon Photonics is of great interest. In the scope of co-integrating III-V devices with CMOS very large scale integration (VLSI), innovative contacts to III-V materials have to be developed. In this paper we study the metallurgical and electrical properties of Ni-based metallizations to n-InP and p-InGaAs. It appears that the integration of both metallizations must be realized at temperatures lower than or equal to 340 °C starting with that on n-InP.

International audience; We present experimental and simulated J-V characteristics of Metal/Insulator/Semiconductor (MIS) junctions aiming at improving the contact resistivity for advanced CMOS nodes. We show that an Atomic Layer Deposition (ALD)-based Al2O3 process may induce a native silicon oxide regrowth leading to an additional tunneling resistance in series. A modelling-based analysis of Metal/Insulator/Insulator/Metal (MIIS) contacts, including the potentially beneficial interfacial dipole, provides a new outlook on high-kappa/SiO2 bilayers for low resistivity contacts.

Auteur correspondant: "philippe.rodriguez@cea.fr"; International audience; In this work, we studied the solid-state reaction between a Ni$_{0.9}$Co$_{0.1}$ film and a silicon substrate. NiCo silicide is considered to substitute Ni-and NiPt-based silicides in 3D integration in order to extend the bottom transistor thermal stability. Thanks to the combined analysis of sheet resistance data, X-ray reflectivity spectra modelling, X-ray diffraction and wavelength dispersive X-ray fluorescence analyses on Ni$_{0.9}$Co$_{0.1}$ /Si samples annealed at various temperatures, we were able to describe the phase sequence of the NiCo silicide formation.

International audience; In this paper, some key fundamental aspects of Metal / Insulator / Semiconductor contacts as well as practical issues occurring with their implementation are reviewed in order to fully comprehend the opportunities and limitations of this approach.

In 3D sequential integration, the top transistor thermal budget must be reduced to preserve bottom MOSFET performance. In order to relax this thermal budget limitation, the thermal stability of the bottom level must be increased, especially for the silicide. In that purpose, Ni0.9Co0.1 alloy is proposed to replace the current Ni0.85Pt0.15 silicide. For the first time, this Ni0.9Co0.1 salicide has been integrated on pMOS FDSOI transistors with state of the art process leading to performance improvements compared to the standard Ni0.85Pt0.15 salicide. In this study, the cobalt incorporation into the salicide has been investigated to enhance its thermal stability.

International audience; Silicon photonics is of great interest as it opens the way to large bandwidth and high data rates. A pioneer Silicon photonics scheme consists in integrating III-V lasers on the SOI substrates containing the passive components. However, key developments are necessary to co-integrate III-V devices with CMOS very large scale integration (VLSI). In this paper we propose a CMOS-compatible integration scheme of contacts (i.e. semiconductor metallization and plug) on III-V surfaces taking into account the limitations fixed by the operating laser device. Based on metallurgical, morphological, optical and electrical studies, processes are submitted and reviewed for the purpose of forming stable and reproducible contacts with low resistivity in a 200 millimeters fab line.

International audience; In this work, we studied the pretreatment of InGaAs layers by employing Ar-and He-based direct plasmas and NH$_3$ , H$_2$ , NF$_3$ /NH$_3$ remote plasmas. All the remote plasmas involved in this study were inadequate to remove the InGaAs native oxides. Moreover, for NF$_3$ /NH$_3$ exposed samples, we noticed the addition of undesirable In–F and Ga–F bonds. Concerning Ar and He direct plasmas, investigations exhibited that both seem to be efficient for removing arsenic oxides whereas the elimination of indium oxides is more effective with Ar plasma. We also studied the addition of hydrogen into He direct plasma and we demonstrated that increasing the H2 content leads to decreasing the removal of arsenic oxides. The impact on indium oxides is also notable as we observed a reducing effect of hydrogen on indium and the emergence of In–In type bonds. Finally, whatever the plasma pretreatment, no degradation of surface morphology and roughness was observed by AFM. The RMS values obtained after surface treatments are similar with the ones acquired for reference samples.

The metallurgical properties of the Ni/n-InP system meet a great interest for its use as a contact in the scope of Photonics laser application. We report the formation of a compositionally non-uniform Ni-In-P amorphous layer during the early stages of the contacts elaboration, which include HCl and Ar+ plasma cleanings prior to the metal DC sputtering. During various heat treatments, the coexistence of the Ni2P and Ni3P binary phases and the Ni2(InP) ternary phase were observed while In release was featured. For temperatures equal to or greater than 350?C we highlighted the formation of In phase. Thanks to RTP and long-time annealing processes, we pointed out the predominance of the diffusion and/or interfacial reactions on the formation of the Ni2P, Ni3P and Ni2(InP) phases and that of nucleation or melting/solidification on the formation of In agglomerates. Display Omitted Modification of the InP surface by the Ar+ pre-cleanGrowth of Ni2P, Ni3P and Ni2(InP) phases associated to Indium release during rapid annealing treatmentsFormation of the Ni2P, Ni3P and Ni2(InP) phases controlled by the diffusion and/or interfacial reactionsFormation of In clusters controlled by precipitation or melting/solidification for temperatures equal to or greater than 350?C

After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650^oC). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.

Ni-GeSn based materials are promising in order to obtain contacts in complementary metal oxide semiconductor and Si photonic devices. In this work, a systematic and comprehensive study of the solid-state reaction between NiPt thin films and Ge0.9Sn0.1 layers is carried out. A particular focus is given on the impact of the addition of 10 at. % of Pt in Ni thin films. In situ X-ray diffraction and in-plane reciprocal space map measurements reveal a sequential growth in which the first phase appearing corresponds to a Ni-rich phase: (Ni0.9Pt0.1)5(Ge0.9Sn0.1)3. Then, at 245 °C, the Ni-rich phase vanishes to the benefit of the mono-stanogermanide phase (Ni0.9Pt0.1)(Ge0.9Sn0.1), which is unstable. At 360 °C, a more stable (Ni1– yPty)(Ge1– xSnx) phase is obtained concomitantly to the formation of PtSnx compounds. Finally, Sn segregation occurs at even higher temperatures. Even if Pt addition in Ni thin films complicates the phase formation sequence, it positively impacts the surface morphology and roughness, delays film agglomeration and Sn segregation, and stabilizes the electrical properties of the stanogermanide in a wide range of temperatures.

The problematics of contacts optimization on Germanium MOSFETs suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals such as Ti on Ge were so far mostly investigated on weakly n-doped samples under pure Thermionic Emission (TE) regime. In this paper, we detail Schottky Barrier Height (SBH) extractions based on contact resistance (Rco) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully-processed GeOI samples with Ti-based contacts, yielding effective barriers of 0.32eV for electrons and 0.15eV for holes. The method provides a good physical understanding of the technological factors impacting their electrical properties, therefore enabling to define paths towards ohmic contact optimization in the context of device integration on GeOI.

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (

International audience; InGaAs, as a channel material, is an attractive option in order to enhance CMOS performances and continue the downscaling of transistors. In order to make reliable InGaAs-based devices, many aspects must be studied. We have studied the silicide-like formation of contacts for the InGaAs's MOSFET's by solid-state reaction of Ni on InGaAs on InP substrates. Precise comprehension of the so-formed material according to annealing temperature is crucial to obtain the desirable quality, stability and low resistivity of the intermetallic.

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

The metallurgical properties of the Ni/n-InP system have been investigated. We report the formation of a compositionally nonuniform Ni-In-P amorphous layer during the DC sputtering metal deposition process which includes an Ar+ cleaning. During various heat treatments the simultaneous appearance of the Ni2P and Ni3P binary phases and the Ni2InP ternary phase were observed. For temperature equal to or greater than 350°C we highlighted the partition and precipitation of In. Thanks to RTP and longtime annealings we pointed out the predominance of diffusion on the formation of the Ni2P, Ni3P and Ni2InP phases and that of nucleation on the partition and precipitation of In.

In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction was properly evaluated by solving the self-consistent case of voltage sharing for an aggressively scaled transistor flanked by two trench Metal/ Insulator/Semiconductor (MIS) contacts. We found that leveraging the Fermi Level depinning via optimized MIS contacts could lead to a +92% drive current (V GS =V dd =0.7V) increase versus a Titanium liner-based silicidation-free approach.