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CMOS technology has always exploited the high thermal stability of Si, which enables high temperature fabrication steps for various device improvements, in particular, for curing oxide defects and hence improving the device stability and reliability. However, with the rise of novel device and architecture concepts such as sequential 3D stacking of Si CMOS tiers in a monolithic integration flow, or the introduction of high-mobility Ge/III–V channels, this paradigm cannot be maintained, and the entire fabrication flow will have to be enabled at a reduced thermal budget. We investigate the current industry standard high-k dielectric, HfO2, showing how its charge trapping behavior evolves when reducing the overall fabrication thermal budget, affecting the positive bias temperature instability (PBTI) of the device. We perform this study focusing on thermal budget ranges of relevance for gate stack development compatible with future technologies. Our finding of reduced reliability at lower thermal budgets (especially <300 °C) is explained in terms of changes in the oxide defect bands, as suggested by physics-based charge trapping modeling. Our results support the hypothesis of multiple microscopic defects contributing to PBTI in HfO2: for low fabrication thermal budgets, the stretched Hf–O–Hf bonds might dominate the charge trapping kinetics, while with post-deposition anneal at temperatures >400 °C, oxygen vacancies might become the dominant species. [ABSTRACT FROM AUTHOR]

In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore’s law to the sub-10 nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS. [ABSTRACT FROM AUTHOR]

Abstract: In this work, we present the impact of standard CMOS-based patterning techniques and more specifically the impact of strip chemistries on the electrochemical behavior of TiN electrodes. As TiN is a material that is both CMOS- and biocompatible, these electrodes are of interest for in vitro and in vivo biomedical applications to interface with electrogenic cells. When scaling down the TiN electrodes to cellular and sub-cellular dimensions, the use of optical lithography in combination with RIE-based (Reactive Ion Etch) patterning will be required. This can be done with standard CMOS processes and tools. However, the TiN etch and more important the subsequent strip of the photoresist are often O2-based. It will be demonstrated that these O2-based chemistries need to be avoided in order to keep the electrode impedance low and its charge injection limit high. The increased surface oxide after exposure to these chemistries decreases the double layer capacitance and reduces the ability of the electrode to transfer charge to the medium and cells. Screening of different strip chemistries, that can be used in the patterning of micrometer sized electrodes, was achieved by electrochemical measurements in combination with XPS analysis on large TiN electrodes. Strip plasmas based on N2/H2 are interesting alternatives to keep the electrode surface intact by reducing the amount of oxygen present at the electrode surface. Moreover, H2O vapor can reduce the surface oxide even further and can lead to lower impedance values and an increased charge storage capacity, beyond the values of the as-deposited layers. The results presented in this paper demonstrate that the scalability of TiN electrodes can be improved significantly when O2-based plasma chemistries are removed from the electrode patterning process. Optimized cleaning after etch and during strip can be beneficial to the overall electrochemical characteristics of the electrode. [Copyright &y& Elsevier]

Abstract: In this work, the impact of the substrate bias on the sense margin and retention behavior in 1T-DRAM bulk FinFET memory cells is discussed. It will be shown that the substrate bias can be used to increase both the sense margin and retention time. For fixed wordline and bitline biasing conditions, a substrate bias can be found where sense margin and retention time are optimal. This substrate bias results from a trade-off between the storage of electrons and holes and the impact of the read-out bias conditions. [Copyright &y& Elsevier]

Abstract: This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance. [Copyright &y& Elsevier]

Abstract: Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased V T statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32nm technology node on, planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET-based multi-gate devices for the 32nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed. [Copyright &y& Elsevier]

Abstract: In this paper specific features of the multiple-gate MOSFETs (MuGFETs) behavior at high temperatures (up to 300°C) are analyzed through measurements, 2D simulations and analytical models of long-channel transistors. The high-temperature evolutions of threshold voltage and subthreshold slope are discussed paying particular attention to the influence of Si film thinning. High-temperature behavior of the threshold voltage and subthreshold slope in MuGFETs is demonstrated, for the first time, to be different from those generally considered for FD SOI MOSFETs. It is shown that the threshold voltage shift with temperature is strongly attenuated in MuGFETs and further decreases with Si film thinning. Then, the deviation of the MuGFET subthreshold slope at high temperatures from the expected ideal linear temperature dependence is analyzed and the possible reasons are discussed. [Copyright &y& Elsevier]

Abstract: In this work, the effective mobility in n- and p-channel FinFETS with silicon oxynitride and HfO2 gate dielectrics and TaN gate electrode is studied as a function of the inversion charge density using a split C-V technique. The mobility behavior in narrow-fin devices is compared to that in quasi-planar wide-fin devices, and the mechanisms responsible for the observed differences are discussed. The devices with HfO2 and silicon oxynitride gate dielectrics exhibit similar mobility behavior. [Copyright &y& Elsevier]

Abstract: In this work, we extend the modified shift and ratio method, originally used for extracting the effective channel length in standard short channel MOSFETs, to the extraction of the fin width in FINFET devices. Using devices with different fin widths, the electrical width of the devices can be extracted. The method is adapted in such a way that it takes into account the difference in mobility due to the different crystal orientation of the fin sidewalls and top surface, the width dependence of the threshold voltage and the influence of the increasing source/drain resistance for narrow fin devices. [Copyright &y& Elsevier]

In this paper, a standard CMOS technology is used to fabricate high performance Si/Si0.68Ge0.32 pMOS devices with thin Si cap layers. Careful fine-tuning of the epitaxial growth conditions and pre-epi surface treatment leads to the deposition of high quality facet free epitaxial layers.As compared to Si-only devices, the Si/Si0.68Ge0.32 devices exhibit strongly enhanced mobilities. For the best devices an increase by a factor of 2.5 can be seen. This enhanced mobility behaviour results in a strong increase of the on-state current and transconductance for devices with a gate length down to 0.13 μm. [Copyright &y& Elsevier]

In this paper, dry etched vertical nanowires (VNWs) are used in transmission line/transfer length analysis to study the contacts of gate-all-around devices for future technology nodes. VNW resistors with Mo and Pd based metal stack contacts to p-InGaAs show Schottky behavior, unlike the planar counterpart. The resistance for Mo contact is higher than Pd, however, Pd was found to form an alloy with InGaAs at temperatures as low as 190 °C, and the length of Pd diffusion into the InGaAs increased at smaller NW dimensions, hindering future scalability. The minimum extracted specific contact resistivity (ρC) values are 1.6 × 10−5 Ω cm2 (Mo) and 4.2 × 10−6 Ω cm2 (Pd) for a doping level of 1 × 1019 cm−3. An apparent dependence of ρC on the NW diameter was also observed. This has been attributed to the surface states under the un-gated region of NW devices and found to dominate at smaller diameters. An analytical model to account for such geometrical effects has also been developed and validated with technology computer-aided design simulations. The analysis presented in this paper effectively captures the 3D aspects of an NW contact at nanoscale dimensions and can be applied irrespective of the semiconductor and contact metal used. [ABSTRACT FROM AUTHOR]

Highlights • Measurements of parasitic capacitance for several front and back biases is possible. • New model of the inversion charge density for several back bias is validated. • Mobility of UTBB‐FDSOI device with short length is assessed for several back biases. • Short FDSOI device mobility depends on the channel edges scattering mechanism. • Mobility reduction suggests edge‐defects from top to bottom of the Si‐Substrate. Abstract In this work we measure the inversion charge density for short UTBB-FDSOI MOSFETs (down to 45 nm) using an accurate method for the extraction of the parasitic components which take into account the effect of the back bias. Based on these results, we propose a modification of the inversion charge density model that uses the simplified Lambert function in order to include the back bias effect. This model is then validated with the experimental data for different gate lengths (from 185 nm to 45 nm). It is shown that this inversion charge model is valid for the mobility extraction and gives very good assessment of the mobility if we know only the IV-characteristic, the threshold voltage (under back bias effect) and the inversion charge capacitance. Finally, this method is used to extract the mobility for short channel devices (down to 40 nm) and it is found that the short channel mobility suffers from degradation even for large back biases. For the shortest device, it is demonstrated that the main source of mobility degradation is caused by oxide charges and interface states located near the S/D extensions and then it is deduced that the mobility reduction for large back biases is related to neutral defects from Si-crystal close to the channel edge. [ABSTRACT FROM AUTHOR]

An industry-friendly approach to fabricate III-V vertical FETs is demonstrated, focusing on n+/i/n + InGaAs stacks grown inside wide-field trenches defined in an oxide layer (field oxide) on 300 mm Si wafers. Two concepts of vertical nanowire patterning are evaluated here, namely: “III-V etch first” and “III-V etch last”. The latter approach is shown to have some key advantages, providing not only a superior profile for the nanowires but also enabling a simplified integration flow. A cyclic methane/hydrogen-based dry etch recipe run in combination with wet clean has been developed to obtain 160–170 nm tall InGaAs nanowires with CDs of about 30–35 nm. Oxygen-based passivation applied in plasma steps is shown to provide a better profile control compared to an ozone-based passivation utilized during wet cleaning. Finally, an optimization of the field oxide recess step is proposed and demonstrated in order to improve the flatness and control of the layers surrounding the vertical wires structure and simplify the further vertical flow processing. [ABSTRACT FROM AUTHOR]

We study in this work the growth and fabrication of top-down highly doped n + InAs(Si)/p + GaSb(Si) Esaki tunneling diodes on (001) GaAs substrates. A careful investigation on the highly mismatched GaSb/GaAs growth is first conducted by means of Reflection High-Energy Electron Diffraction (RHEED), Atomic Force Microscopy (AFM), and X-Ray Diffraction (XRD) analyses. These results are expected to pave the way to methods for III-Sb buffer layer's integration with low threading dislocation (TD) densities. A comparison between AFM, XRD, defect revealing by chemical etching and transmission electron microscopy (TEM) is then presented to calculate the precise TD density and its influence on the device structure. In the last part, we report on first operating sub-30 nm III-V vertical NW tunneling devices on (001) commercial GaAs substrates. [ABSTRACT FROM AUTHOR]

Abstract: This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gm max, and analog figures of merit, such as transconductance over drain current ratio, Gm /ID , output conductance, GD , Early voltage, V EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher Gm max. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model. [Copyright &y& Elsevier]

This work investigates the effects of high-energy neutrons and γ-rays on multiple-gate FETs with different geometries (notably gate lengths down to 50 nm). The impact of radiation on device behavior is addressed through the variation of parameters such as threshold voltage, subthreshold slope, transconductance maximum and DIBL. It is shown that degradations caused by γ-rays and high-energy neutrons with similar doses are largely similar. It is revealed that, on the contrary to the generally-believed immunity to irradiation, very short-channel FinFETs can become extremely sensitive to the total dose effect. The possible reasons are discussed. [ABSTRACT FROM AUTHOR]

Abstract: This paper investigates, for the first time, the influence of high-energy neutrons on Multiple-Gate FETs (MuGFETs) with various gate lengths and fin widths. Neutron-induced degradation is addressed through the variation of major device parameters such as threshold voltage, subthreshold slope, maximum transconductance and DIBL. We demonstrate that high-energy neutrons result in total-dose effects largely similar to those caused by γ- and proton-irradiations. It is shown that, contrarily to the generally-believed immunity to irradiation, very short-channel MuGFETs can become extremely sensitive to the total-dose effect. The possible reasons of such length-dependent neutron-induced degradation are discussed and finally related to gate edges. [Copyright &y& Elsevier]

Abstract: In this work the influence of Selective Epitaxial Growth (SEG), high-k gate-dielectric and rotation of the channel on the low frequency (LF)-noise is investigated. The carrier number fluctuations dominate the 1/f noise for all the devices studied. An unusual effective trap density profile is found. It decays with a larger distance from the interface. This implies a higher trap density in the interfacial SiO2-layer, compared with the high-k dielectric. The shape of the profile is different for a HfSiON gate-dielectric compared with a HfO2 gate-dielectric. Higher trap densities are found for the latter. The Selective Epitaxial Growth (SEG) and channel orientation show only a negligible impact on the noise behavior when a HfSiON-dielectric is used. [Copyright &y& Elsevier]

Abstract: At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 ]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (V T) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (W fin) and gate length (L g) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (R SD) engineering become more challenging. In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial R SD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10nm. [Copyright &y& Elsevier]

The proton irradiation effects on n-MuGFET devices with three different geometries (single fin, wide fin and multiple fin) are studied. Also, the effect of tensile strain in the fin on the radiation behavior is investigated. A fundamental difference in the radiation behavior between the non-strained and the strained devices is found. The degradation of the strained devices is most affected by the mobility decrease of the backside transistor. The non-strained devices show a much lesser back gate mobility degradation. For these devices the creation of positive oxide traps is dominant. This shifts the onset of the back channel to lower gate voltages, inducing a transconductance increase at intermediate gate voltages. This effect is less pronounced for single fin MuGFETs. At higher gate voltage, the transconductance decreases for the strained and increases for the non-strained transistors. [ABSTRACT FROM AUTHOR]

Abstract: In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO2 than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25nm. The possible reasons for the observed effect are discussed. [Copyright &y& Elsevier]

Abstract: Inherently smaller cross-sectional area of heavily doped source/drain regions (HDDs) in multiple gate transistors is known to give rise to a higher contact resistance between Si and HDD silicide as compared to a planar transistor with similar width of the Si channel. In order to characterize the contact resistance, multiple gate FETs have been fabricated with fin widths and gate lengths down to 18 and 45nm, respectively. Experiments performed by varying layout and technology parameters show that Nickel silicide forms wrapped contacts around HDDs. Further, the silicidation process is shown to be fully siliciding HDDs in devices with narrow fins, where a selective epitaxial growth of Si has been performed in HDDs. [Copyright &y& Elsevier]

The impact of the short gate length on the drain current and low frequency (LF) noise in GaN/AlGaN metal-oxide-semiconductor high-electron-mobility field-effect-transistors has been studied. In some short devices, a parasitic subthreshold current is observed. In this article, the origin of parasitic subthreshold currents were explored using LF noise and trapping transient measurements. The LF noise power spectral density (PSD) of the devices without parasitic drain current decreased monotonically with the decrease of the drain current, while the PSD of the device with the parasitic drain current strongly increased for lower drain current. The 1/f1.5 noise corresponding with the parasitic leakage can be explained by the level broadening of generation-recombination centers in the GaN channel. This is confirmed by the trapping transient measurements, revealing a temperature-independent time constant, associated with the leakage path in short channel transistors, exhibiting the subthreshold humps. [ABSTRACT FROM AUTHOR]

In this work, we demonstrated considerable enhancement of the transport characteristics of n-type Al2O3/In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (n-MOSFETs) with the assistance of in situ NH3/N2 remote-plasma (RP) treatment. According to the measurement and simulation results, the RP treated sample shows superior device performances as compared to the control sample without plasma treatment including (a) improved on-current (Ion) from 8.5 mA/mm to 17 mA/mm, (b) improved transconductance (Gm) from 16.05 mS/mm to 28.52 mS/mm, (c) suppressed subthreshold swing from 189 mV/dec to 170 mV/dec, (d) suppressed drain induced barrier lowering from 36 mV/V to 28 mV/V, (e) intensified peak effective mobility (μeff) from 1896 cm2 V−1 s−1 to 2956 cm2 V−1 s−1, and (f) reduced acceptor-type density of interface trap state (Dit,A) to 44%. By using TCAD simulation, device output performance is found to be dramatically impacted by the trap state (especially acceptor-type) at the Al2O3/InGaAs interface. [ABSTRACT FROM AUTHOR]

To enable CMOS-compatible GaN HEMTs for the next generation of communication systems (5G and beyond), a low gate resistance is of great importance since it directly affects the RF power gain and ƒMAX of the transistor. In this article, the impact of various gate-metal stacks on the gate resistance and RF performance of the devices is studied. The optimized Ti-free gate-metal process leads to ƒMAX enhancement up to ~50% for devices scaled down to 0.32-μm gate lengths. The gate resistance for the T-shaped gate is modeled from the S-parameters and validated on various gate field plate geometries. The tradeoff between the gate resistance and the parasitic capacitance in GaN HEMTs is highlighted in this case. [ABSTRACT FROM AUTHOR]

This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in shallow trench isolation trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon. [ABSTRACT FROM AUTHOR]

In this article, GaN/AlGaN metal–oxide–semiconductor high-electron-mobility field-effect transistors (MOSHEMTs) fabricated on high-resistivity Si (111) substrates have been evaluated using low-frequency (LF) noise measurement. The noise power spectral density (PSD) of devices with different lengths and channel orientations has been characterized in linear operation. No noticeable differences in the electrical and noise PSD characteristics have been observed between the GaN [1100] and [1120] channel orientations. While most devices are dominated by 1/ƒ noise, originating from number fluctuations, for long devices (L ≥ 1.1~μm), additional generation–recombination (GR) noise has been observed, originating from traps in the GaN layer. [ABSTRACT FROM AUTHOR]

This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (Ad), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest Ad, while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trap-assisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher Ad and ON-state current than Point TFETs. [ABSTRACT FROM AUTHOR]

This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high-k last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Six)Ge1-xOy, which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced DIT, and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum VOV of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm-Lg n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack. [ABSTRACT FROM AUTHOR]

In this work, Gate-All-Around Nanowire MOSFETs have been studied at very low temperatures. DC behaviors have been investigated in the linear operation and saturation regions, giving access to several analog parameters. Static characteristics at 4.2 K and low polarization exhibit step- like variations of the drain current, which can be linked to energy subband scattering. First results on the impact of quantum transport mechanism on the low frequency noise are shown. Finally the low frequency noise spectroscopy has led to the identification of silicon film traps. [ABSTRACT FROM AUTHOR]

This paper reviews some of the key doping strategies pursued for scaled finFET devices fabrication, addressing several of the critical integration challenges faced by this device architecture with regard to junction engineering, parasitics and series resistance control and their impact on device performance, reliability and variability. We will therefore look into the extendibility possibilities of using conventional doping techniques such as ion implantation, explore the use of novel methods to enable conformal doping of the thin body of the devices, and also evaluate junctionless vs. inversion-mode type of transistors for gate-all-around nanowire FETs, which can essentially be considered as the ultimate scaling limit of triple-gate finFETs. [ABSTRACT FROM AUTHOR]

Low frequency noise measurements are used as a non-destructive diagnostic tool in order to evaluate the quality of the gate oxide and the silicon film of sub-10 nm triple-gate Silicon-on-Insulator (SOI) FinFETs. It was found that the carrier number fluctuations explain the 1/ f noise in moderate inversion for n- and p-FinFETs, which allows estimating the gate oxide trap densities. The noise spectroscopy with respect to temperature (study of the generation-recombination noise) led to the identification of the traps located in the transistors silicon film. [ABSTRACT FROM AUTHOR]

The transfer characteristic at room temperature of FinFETs processed for sub-10 nm technologies could always be explained by solving Poisson equation throughout the channel – dielectric interface. Various methods for the MOSFET parameters estimation are proposed in the literature. In this paper, the electrical parameters extraction technique based on the Y-function methodology is reminded. Low frequency noise is presented considering three major noise sources: 1/ f noise associated to carrier trapping-detrapping in the gate oxide, channel carrier mobility fluctuations and generation-recombination noise related to traps located in the depletion zone of the device. Theory and methodology in order to identify the 1/ f noise mechanism and to have information of the process induced traps in the silicon film using the noise spectroscopy technique are revisited. [ABSTRACT FROM AUTHOR]

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm. [ABSTRACT FROM AUTHOR]

We systematically studied the effects of metal electrodes on high-k/InGaAs gate stacks and observed that the remote reactions--both oxidation and reduction--at the interface between the high-k dielectrics and InGaAs were thermodynamically initiated by the metal electrodes. Metal electrodes with negative Gibbs free energies (e.g., Pd) resulted in the oxidation of the InGaAs surface during the forming-gas annealing. In contrast, with TiN electrodes, which have a positive Gibbs free energy, the native III-V oxides underwent the reduction between the high-k dielectrics and InGaAs. We demonstrated that the reduction of native III-V oxides by metal electrodes improved the interface quality of the high-k/InGaAs gate stacks and produced an interface trap density (Dit) at the mid-gap with a value as low as 5.2×1011 cm-2 eV-1 with a scaled capacitanceequivalent thickness. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties. [ABSTRACT FROM AUTHOR]

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14. [ABSTRACT FROM AUTHOR]

Two planar Ge-based MOSFET structures were analysed for n- and p-type transistors with tensile and compressive strain implemented in the <110> channel direction using source/drain stressors. Strain profiles measured by nano-beam diffraction (NBD) have been compared with Sentaurus process simulations. The TCAD simulations were tuned with the actual process using NBD measurements, resulting in a more realistic simulation and, therefore, a more reliable interpretation is now possible. dark-field scanning transmission electron microscopy images added to the strain profiles returned interesting results about the Ge virtual substrate condition and how it disturbs the NBD readings due to the presence of extended defects in strain relaxed Ge buffer layers. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Abstract: Strained Ge channel PFETs have the potential to outperform state-of-the-art strained Si channel PFETs. This paper describes the integration aspects for strained Ge channel devices based on TCAD simulations and experimental observations. The most scalable way of introducing channel stress is by the use of Si1− x Ge x strain relaxed buffers (SRB) and/or high Ge-content source/drain stressors, selectively grown in STI. Reduction of the thermal budget, damage and Ge loss during subsequent processing are key to maintain the high strain in the Ge channel till the end of processing. [Copyright &y& Elsevier]

We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10 smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In0.53Ga0.47As, InAs, and a modified version of In0.53Ga0.47As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply voltages. For p-TFET, a strongly confined n-i-p or n-p-i-p configuration is therefore recommended, as well as a tensily strained line-tunneling configuration. [ABSTRACT FROM AUTHOR]

Highlights: [•] The benefit of the use of strain engineering techniques is kept at 10K operation. [•] The carrier number fluctuations dominate the 1/ noise in weak inversion. The parameter variation with the temperature (independent from strain and gate length) shows that the spatial distribution of traps in the oxide is not homogenous and that the active trap density increases towards the interface. [•] The access resistance noise contribution on the total noise, which prevail in strong inversion operation, originates from mobility fluctuations at 300K while at 10K seems to have a trapping - detrapping origin. [Copyright &y& Elsevier]

Highlights: [•] Si cap passivation on Ge shows low border trap response. [•] The Si cap passivation is also suitable for Ge nMOS applications. [•] Low D it at E c can be achieved by tuning the amount of Si at the interface. [•] A dry O3 process can be used to control the amount of Si that is oxidized. [Copyright &y& Elsevier]

In this work, the DC behavior of AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MO(I)SHEMTs) with two different gate dielectrics (Al 2 O 3 and Si 3 N 4) is analyzed through the experimental comparison of their basic and analog parameters. The transistors with Si 3 N 4 insulator are more closely related to the normally-off devices (less negative threshold voltage) and less affected by the short channel effects (better DIBL behavior). Although the devices with Si 3 N 4 layer presented a double conduction, that results in anomalous transconductance behavior, it is more suitable for analog applications since the Al 2 O 3 devices suffer large self-heating. The very high gate leakage of Si 3 N 4 MISHEMT degrades the subthreshold regime, which decreases the transistor efficiency at weak inversion. On the other hand, the devices with Si 3 N 4 insulator present relatively large Early voltage and consequently high intrinsic voltage gain in strong inversion, reaching 84 V/V (38.5 dB). Even at high temperatures the intrinsic voltage gain is practically the same, degrading only 1.5 dB from 25 °C to 150 °C for a long channel device. [ABSTRACT FROM AUTHOR]

The low frequency (LF) noise has been studied in n-channel triple-gate bulk fin Field-Effect Transistors (FinFETs), which are developed for one-transistor (1T) memory applications. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components, associated with generation–recombination (GR) noise. Both gate-voltage-dependent and gate-voltage-independent GR noise peaks have been found, which are assigned to gate oxide traps or traps in the silicon fins, respectively. In addition, excess \1/f noise in weak inversion has sometimes been observed and is ascribed to surface-roughness fluctuations. Overall, the gate oxide quality seems to be the major contributor to the LF noise and not the channel and source–drain engineering investigated here. [ABSTRACT FROM PUBLISHER]

Abstract: This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL. On the other hand, the impact of the gate dielectric on the GIDL for p- channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed. [Copyright &y& Elsevier]

Abstract: In this paper, the low frequency noise was studied from 100K up to room temperature in n-channel triple-gate FinFET transistors fabricated on silicon on insulator (SOI) substrates. It was found that the noise spectra contain 1/f and Lorentzian components, which can be analyzed using the standpoint of the number fluctuation by generation–recombination of carriers due to traps that can be located either at the gate oxide/Si film interface or in the silicon depletion film. The variations of the low frequency noise versus temperature allow to evaluate the quality of the gate oxide interface, to identify traps in the silicon film and to make a correlation between the observed traps and some technological steps. Moreover, some additional process steps used to boost the device performances seem to increase the trap densities in the film with no significant impact at the gate oxide/Si film interface. [Copyright &y& Elsevier]

Abstract: A comparative investigation of high-energy neutrons effect on strained and non-strained devices with different geometries is presented. Both single-gate planar and multiple-gate (MuG) silicon-on-insulator (SOI) devices are considered. Device response to the neutron irradiation is assessed through the variations of threshold voltage and transconductance maximum. The difference between strained and non-strained device response to the high-energy neutrons exposure is clearly evidenced. The reasons for such a difference are discussed. Analysis of the experimental results allows for suggesting that strain relaxation is one of the probable causes. [Copyright &y& Elsevier]

We report the observation of lifetime-enhanced transport (LET) based on perpendicular valleys in silicon by transport spectroscopy measurements of a two-electron system in a silicon transistor. The LET is manifested as a peculiar current step in the stability diagram due to a forbidden transition between an excited state and any of the lower energy states due to perpendicular valley (and spin) configurations, offering an additional current path. By employing a detailed temperature dependence study in combina- tion with a rate equation model, we estimate the lifetime of this particular state to exceed 48 ns. The two- electron spin-valley configurations of all relevant confined quantum states in our device were obtained by a large-scale atomistic tight-binding simulation. The LET acts as a signature of the complicated valley physics in silicon: a feature that becomes increasingly important in silicon quantum devices. [ABSTRACT FROM AUTHOR]

Abstract: This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation, TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V EA) values which resulted in a lower voltage gain. The 45° rotated devices have a smaller V EA than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (100) sidewall orientation, compensates this V EA degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. [Copyright &y& Elsevier]