A wafer-scaled III-V vertical FET fabrication by means of plasma etching.

An industry-friendly approach to fabricate III-V vertical FETs is demonstrated, focusing on n+/i/n + InGaAs stacks grown inside wide-field trenches defined in an oxide layer (field oxide) on 300 mm Si wafers. Two concepts of vertical nanowire patterning are evaluated here, namely: “III-V etch first” and “III-V etch last”. The latter approach is shown to have some key advantages, providing not only a superior profile for the nanowires but also enabling a simplified integration flow. A cyclic methane/hydrogen-based dry etch recipe run in combination with wet clean has been developed to obtain 160–170 nm tall InGaAs nanowires with CDs of about 30–35 nm. Oxygen-based passivation applied in plasma steps is shown to provide a better profile control compared to an ozone-based passivation utilized during wet cleaning. Finally, an optimization of the field oxide recess step is proposed and demonstrated in order to improve the flatness and control of the layers surrounding the vertical wires structure and simplify the further vertical flow processing. [ABSTRACT FROM AUTHOR]