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This work presents a detailed RF characterization of 28-nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (ft) and maximum oscillation frequency (fmax), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ~130 GHz in ft and ~75 GHz in fmax is observed for the shortest device (25 nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28-nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied. At liquid nitrogen temperatures, 30% to 200% enhancement of drain current, Id, and maximum transconductance, gm_max, values are demonstrated. Current gain cutoff frequency, fT, increase by about 85 GHz is shown. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This study suggests 28 nm FDSOI as a good contender for future read-out electronics operated at cryogenic temperatures (as e.g. around qubits or in space).

This paper presents detailed RF characterization of 28-nm FDSOI nMOSFETs at cryogenic temperatures down to 77 K. Two main RF figures of merit (FoM), i.e., current gain cutoff frequency ( $f_{T}$ ) and maximum oscillation frequency ( $f_{\max }$ ), as well as elements of small-signal equivalent circuit are extracted from the measured S-parameters. Increases of $f_{\textit T}$ and $f_{\max }$ by about 85 GHz and about 30 GHz, respectively, are demonstrated at 77 K. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This paper suggests 28-nm FDSOI as a good candidate for future cryogenic applications.

This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.

This work investigates the low-frequency noise performance of a long-channel UTBB FD SOI nMOS transistor operated in triode region as typically used for MOSFET-C filter applications. Measurements of the low-frequency noise have been performed over a large temperature range (25–125°C) at different constant currents above threshold, as a function of the back-gate bias. It is highlighted that in such case, 1/f noise power is dominant, however sufficiently low, in the frequency range of interest for the filters, i.e. below 1 MHz. Noise power strongly reduces with temperature and slightly with positive back-gate bias, which is adequate for the filter tuning.

This work studies, for the first time to the authors’ best knowledge, the self-heating (SH) effect in ultra-thin body ultra-thin BOX (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, is employed to assess SH parameters and related degradation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

International audience; The negative bias temperature instability (NBTI) is investigated in ultrathin body ultrathin box (UTBB) fully depleted silicon-on-insulator (FD-SOI) p-MOSFETs with zero back gate bias and small drain bias voltage. The threshold voltage shifts during stress at different temperatures and gate bias voltage conditions show that the NBTI is dominated by the trapping of holes in preexisting traps of the gate dielectric, while the recovery transient follows a logarithmic-like time dependence. Considering the hole-trapping/detrapping mechanisms, NBTI modeling has been proposed capturing the temperature and gate voltage dependence.

A detailed study of the hot-carrier degradation in nano-scale fully depleted ultra-thin body and buried oxide n-MOSFETs is presented. The degradation mechanisms were identified based on static current-voltage measurements. The degradation of the transistor was explained by considering generation of traps at the gate dielectric/Si interface and traps located within a tunneling distance of the interface. All stress parameters are considered describing with semi-empirical relations their impact on the transistor parameters. Based on our analytical compact model, we propose an aging hot-carrier model predicting with good accuracy the device degradation stressed under different bias conditions using a unique set of model parameters. Display Omitted The hot-carrier degradation of nanoscale UTBB FD-SOI n-MOSFETs has been investigated under different drain and gate bias stress conditions.The degradation mechanisms have been identified by studying the static current-voltage characteristics measurements.The impact of the HC degradation on the device parameters has been expressed with semi-empirical models in terms of the stress time, channel length, drain bias and gate bias.Based on our analytical compact model, HC aging model is proposed enabling to predict the device degradation stressed under different bias conditions, using a unique set of few model parameters determined for each technology through measurements.

This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD-SOI) planar ultra-thin body and BOX (UTBB) MOSFETs for high frequency applications. All parasitic elements such as the parasitic gate and source/drain series resistances, total capacitances are extracted and their effects on RF performance are analyzed and compared with previous work on similar devices. Two main RF figures of merit (FoM) such as the current gain cut-off frequency ( f T ) and the maximum oscillation frequency ( f max ) are determined. It is shown that f T of ∼280 GHz and f max of ∼250 GHz are achievable in the shortest devices. Based on the extracted parameters, the validation of the small-signal equivalent circuit used for modeling UTBB MOSFETs is investigated by comparing simulated and measured S -parameters.

This work presents a detailed RF characterization of 28 FDSOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e. current gain cutoff frequency (f T ) and maximum oscillation frequency (f max ), as well as parasitic elements of the small-signal equivalent circuit are extracted from the measured S-parameters. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28 FDSOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.

This work presents, for the first time to our best knowledge, RF characterization of 28 nm FDSOI CMOS process at cryogenic temperatures including extraction of parasitic elements of small-signal equivalent circuit and two main RF Figures of Merit (FoM), i.e. current cutoff frequency (fT) and maximum oscillation frequency (fmax). Increases of fT and fmax by about 85 GHz and 30 GHz, respectively, are demonstrated at cryogenic temperatures. The observed behavior of RF FoMs versus temperature is analyzed in terms of small-signal equivalent circuit elements. This study suggests 28 nm FDSOI as a good candidate for future cryogenic applications.

This work presents a detailed characterization of 28 nm FDSOI CMOS process at cryogenic temperatures. Electrostatic, Analog and RF Figures of Merit (FoM) are studied for the first time to our best knowledge. At cryogenic temperatures, 20–70% enhancement of drain current, Id, and maximum transconductance, gm_max, values as well as up to 100 GHz increase of cut-off frequency, fT, are demonstrated. Temperature behavior of analog and RF FoMs is discussed in terms of mobility and series resistance effect. This first study suggests 28FDSOI as a good contender for future read-out electronics around qubits.

In this work self-heating and its effect on analogue device parameters are compared in 28 nm technology bulk and FDSOI MOS devices. It is shown that for self-heating characterisation in advanced MOSFETs the RF extraction technique is more suitable than the pulsed I – V . It is found that the thermal resistance is ∼3.4 times higher and the temperature rise is ∼2.5 times higher in 28 nm gate length FDSOI than in bulk. However, in spite of stronger self-heating, FDSOI devices outperform bulk over a wide frequency range. Moreover, device parameters degradation with temperature is attenuated in FDSOI transistors.

This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance gm, the output conductance gd, the intrinsic gain Av and the cut-off frequencies fT and fmax. Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, gm–Av analogue metric is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that fT of 280 GHz and fmax of 250 GHz are reachable in the shortest devices. These values are compared to those of the first generation of UTBB devices through the effect of parasitic elements.

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150 °C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.

This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers morphology has been designed to achieve maximum performance benefits. Both digital, analog and RF performances are exposed, and compared to 28LP gate-first technology. We evidence that FDSOI brings energy efficiency digital and AMS/RF breakthrough for IoT.

International audience; The hot carrier (HC)-induced traps in nanoscale fully depleted ultrathin body and buried oxide nMOSFETs are investigated by low-frequency noise (LFN) measurements in the frequency and time domains. The measured noise spectra are composed of 1/f and Lorentzian-type components. The Lorentzian noise is due to either generation-recombination noise or random telegraph noise (RTN). Based on the LFN results, the effect of the HC stress on fully depleted silicon-on-insulator MOSFETs is investigated after short- and long-time stress. The capture and emission time constants responsible for the RTN noise were calculated as the average duration time of the high/low drain current state, respectively. Analysis of RTN traps detected in fresh and HC-stressed devices indicates that the RTN amplitude is uncorrelated to the trap time constants, i.e., the impact of the trap depth from the interface is masked by that of the trap location over the channel. The overall results lead to an analytical expression for the RTN amplitude, enabling to predict the RTN changes from the subthreshold to the above-threshold region.

Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from −40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120µm2 and 0.152µm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120µm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.

We present a 65nm RF SOI CMOS technology, targeted as Low Power (LP) to serve mobile applications. The integration has been made on High Resistive (HR) back substrate 300mm SOI wafers from SOITEC to improve performances in high frequency range, compared to bulk [1, 2]. For the first time, low leakage SRAM (Isb< 10pA at 0.9V, 25{degree sign}C, for 0.62µm2 and 0.52µm2 cells) are integrated on these HR wafers, and the paper reports a 30% power reduction in operation for a given maximum speed, compared to similar SRAM design on bulk. Furthermore, we have demonstrated a 21% measured power-delay product reduction compared to bulk, at 125{degree sign}C, on loaded ring oscillators.

International audience; An analytical drain-current compact model for lightly doped short-channel ultrathin-body and box fully depleted silicon-on-insulator MOSFETs with back-gate control is presented. The model includes the effects of drain-induced barrier lowering, channel-length modulation, saturation velocity, mobility degradation, quantum confinement, velocity overshoot, and self-heating. The proposed model has been validated by comparing with the experimental transfer and output characteristics of devices with the channel lengths of 30 and 240 nm and with back bias varying from -3 to +3 V. The good accuracy of the model makes it suitable for implementation in circuit simulation tools.

This work presents a comparison of parasitic elements (capacitances and resistances) in a view of their effect on RF Figures of Merit (FoM) in 28 nm fully-depleted silicon-on-insulator (FD SOI) ultra-thin body and buried oxide (UTBB) MOSFETs and their Bulk counterparts. Complete set of small-signal equivalent circuit elements (both “intrinsic”, i.e. device related and “extrinsic”, i.e. parasitic) are extracted from S-parameters measurements in a frequency range up to 40 GHz. It is shown that detrimental/harmful effect of parasitics, particularly capacitances, is stronger in 28 nm bulk technology compared to 28 FD SOI.

session poster; International audience; The HC degradation of nanoscale FD-SOI n-MOSFETs has been investigated under the worst bias stress conditions (Vds,stress = Vgs,stress). At high stress voltages the hot carriers injected into the gate dielectric are the main degradation mechanism, superseding the interface degradation. The proposed degradation mechanisms are supported with the interface and gate dielectric trap properties extracted from LFN measurements.

session poster; International audience; A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with F T = 160 GHz for LP and 280 GHz for GP nMOS transistors.

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm2) single p-well (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. The results from a 140kb programmable dynamic SRAM characterization test module provide both information about location and cause of failures as well as power and performance by mimicking system operating conditions over a wide supply voltage range. A 410mV minimum operating voltage and less than 310mV data retention voltage with a leakage current close to 100fA/bitcell are measured. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.

This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD SOI) ultra-thin body and buried oxide (BOX) (UTBB) MOSFETs for high frequency applications. RF figures of merit (FoM), i.e. the current gain cut-off frequency (f T ) and the maximum oscillation frequency (f max ), are presented for different transistor geometries. The parasitic gate and source/drain series resistances, as well as capacitances and their effect on RF performance are analyzed.

Enabling high speed SRAM operation at low voltage is typically limited by variability and low device drivability. Most of the reported low-voltage SRAM bitcells show significant area penalty and low performances. This paper proposes a Mixed-Single Well (MSW) 8T SRAM bitcell, which takes advantage of wide back bias voltage range capability of ultra-thin body and box (UTBB) FD-SOI technology The bitcell is evaluated in 28nm using the read-after-write (RAW) dynamic metric which overcomes the limitations of standard readability (RA) and writeability (WA) approaches. It is demonstrated that body biasing tuning enables operation of the proposed bitcell at approx. 5.6s at 0.4V with over 100MHz.

Inter-die variability of analog figures of merit of ultra-thin body and buried oxide (UTBB) FDSOI MOSFETs was studied in a wide frequency range. We demonstrate that variability in the entire frequency range is small and does not exceed 5%, which is considerably less than in previously published results on SOI FinFETs. An effect of frequency on the analog figures of merit variability is discussed and preliminary explanation is proposed.

This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance g m , the output conductance g d , the intrinsic gain A v and the cut-off frequencies f t and f max . Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, g m -A v analogue metrics is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that f t reaches ∼270 GHz in the shortest devices.

We designed an addressable transistors array to analyse local variability at the wafer scale. On FDSOI substrates, we measure no impact of the silicon thickness variations on short channel transistors, and demonstrate that the impact on large area transistors is no more visible when the Tsi is well controlled.

In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology.

This work highlights the way to optimize the speed/power performance of the planar FDSOI technology at the 28nm node and beyond. The combination of gate length shrink and spacerO increase leads to 13% delay decrease and 15% dynamic power saving at same speed through capacitance reduction. It demonstrates that, as far as the access resistance penalty is kept reasonably low, increasing the spacerO is highly efficient to boost AC performance in FDSOI.

This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies [1].

Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.

International audience; Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for both interfaces.

International audience; Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530µA/µm @ Ioff=100nA/µm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12µm2 bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.

In this paper, we present, for the first time, a thorough investigation of low frequency noise (LFN) and statistical noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. The experimental results are well interpreted by Monte-Carlo LFN simulations based on the random spatial and energy distribution of discrete traps in the gate dielectric. Our results clearly indicate that the LFN variability of 28nm FD-SOI CMOS technology is improved as compared to previous 45nm and 32nm bulk CMOS technologies.

In this paper the results obtained for a new process flow that integrates a high performance flash cell for automotive application with a state of the art 65nm CMOS have been presented. Despite the several specific process steps introduced for the first time on embedded technologies, the MOS performances have not been impacted by the integration of the Flash cell and the related HV MOS and the results obtained on a 4Mbit Flash array are very promising.

As SRAM integration scheme becomes more and more aggressive in term of development time, supply voltage and geometric dimension, parameter extraction techniques need to be continuously upgraded to ensure the best support for technology development. An innovative approach for write-margin extraction has recently been published at the ISSCC'2006 conference. This approach makes use of test structure giving access to internal node. Here, this approach is evaluated through our 65 nm process and it is shown that the layout and probing of the innovative test structure induces a write delay. As a consequence an adaptation of this innovative methodology is proposed. The new combined solution gives promising results, in terms of accuracy and spread, to better follow the process development of advanced SRAM.

In this work, we report on the integration of 30nm gate length CMOS devices fabricated using laser spike annealing (LSA). Considerably improved short channel effects and drive current (+10% Ion at constant Ioff for NMOS) are demonstrated on samples using LSA. Excellent IonIoff characteristics (Ion = 940 muA/mum Ioff = 200 muA/mum for NMOS and Ion = 390muA/mum Ioff = 50 nA/mum for PMOS at Vdd = 1 V) are measured that are at the leading edge of the state of the art. Moreover, an enhanced dynamic behavior (-6% in ring oscillator delay) and improved characteristics of high density SRAM bit-cells (+24% Icell for the same 1sb) are reported. These results demonstrate the potential of LSA in the perspective of 30 nm device integration of a 45 nm bulk CMOS platform

This work highlights the realization and 0.248/spl mu/m/sup 2/ to 0.334/spl mu/m/sup 2/ SRAM bit-cells with conventional bulk technology based on 19/spl Aring/ CET SiON gate oxide, poly-silicon gate electrode, and mobility enhancement techniques for both nMOS and pMOS. High density critical lithography levels have been exposed with e-beam direct writing thus contributing to the overall cost-effectiveness of the technology.

This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.

This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at V/sub dd/=0.9 Volt using a conventional nitrided gate oxide dielectric. A comparison between offset spacer and PLAsma Doping (PLAD) is made for the transistor characteristics with very promising V/sub th/-L/sub d/ and V/sub th/-W/sub d/ profiles measured. Lithography employed a combination of both optical lithography and e-beam imaging. The BEOL integration used a conventional low K dielectric with copper metallization.

A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 /spl mu/m/sup 2/ bit-cells with 240mV of SNM and 35 /spl mu/A of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 /spl mu/A/ /spl mu/m and 400 /spl mu/A/ /spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/ = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. /spl mu/m) and analog voltage gain factor (G/sub m//G/sub d/>2000 for L = 10 /spl mu/m) at the leading edge for this process technology. NBTI criteria at 125/spl deg/C for both LP and GP transistors are presented and characterized at overdrive conditions.

The impact of the gate leakage current on long MOS transistor characterization is investigated in this paper. Particularly for first order parameter extraction, a new method is proposed here to rid the gate current on advanced technologies with thin gate oxides. In linear and in strong inversion regimes, we first demonstrate experimentally a 50/50 partition of the gate current between source and drain nodes. TCAD simulations performed for several oxide thicknesses and biases also confirm this partition. The intrinsic channel current of the MOS transistor can then be isolated to extract first order parameters, especially in the case of large area devices which strongly suffer from gate leakage. We show that this I/sub G/ correction permits to extract these parameters in a more consistent way. Finally, we evaluate the extraction error induced by the gate leakage current for varying oxide thicknesses and channel lengths.

This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16/spl Aring/ EOT-70nm transistors (standard process) or 21/spl Aring/-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1 Mbit SRAM instances, based on a highly manufacturable 6T 1.36/spl mu/m/sup 2/ memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.

We report a detailed experimental and theoretical investigation of the effect of residual strain, and strain relaxation, which manifests itself at the Si/SiO$_{2}$ interfaces in commercial silicon-on-insulator (SOI) wafers. SOI material is made of a single-crystal silicon overlayer (SOL) on top of an insulator (buried SiO$_{2}$ layer) sitting on a handle silicon wafer. Infrared reflectivity spectra show that the buried SiO$_{2}$ layer relaxes continuously when thinning the SOL. At the same time the SOL surface roughness and the linewidth of optical phonons in Si near the Si/SiO$_2$ interface (probed by micro-Raman specroscopy) increase. In the as-delivered wafers, this comes from a slight expansion of Si on both sides of the buried SiO$_{2}$ layer which, conversely, is compressed. Thinning the SOL modifies these initial equilibrium conditions. To get quantitative results, we have modeled all our Raman spectra using a theory of inhomogeneous shift and broadening for optical phonons, which takes into account the phonon interaction with the static strain fluctuations. From the variation of linewidth versus interface distance, we have found that the mean squared strain continues to relax in the bulk of the wafer through a depth on the order of several $\mu m$. We also show that the SOL surface roughness is related to strain fluctuations near the Si/SiO$_2$ interfaces., Comment: 28 pages, 11 figure, to be published in Phys. Rev. B (Nov 15 2000)