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The parasitic effect inside through-silicon via (TSV) packaging under radio frequency (RF) operation may cause abnormal signals in circuit performance. On the bases of a self-developed deembedding technique, we investigated the high-frequency characteristics of a typical TSV structure through direct measurements. To this end, a silicon substrate layout was first designed and constructed, followed by packaging mounting to build a suitable setting for RF measurements. Behaviors up to 3 GHz on different circuit segments in an actual TSV packaging were then measured directly by using an RF-inductance, capacitance, and resistance (LCR) meter, and R, L, and impedance (Z) data for test structures were then extracted and compared with those reported in the literature. To study the environmental effect on the RF properties of the TSV test samples, we monitored behaviors during a temperature-humidity reliability test.

Flexible thermoelectric (TE) products that convert temperature difference into electrical energy can be used as textile materials to harvest human body heat into electrical power for portable, low-power microelectronic products. To this end, this study investigated a newly developed electrospinning process for producing flexible TE films. After electrospinning, thermoelectric properties of the test samples were extracted through a self-developed measurement apparatus for simple, accurate, and direct thermoelectric measurements. We then compared the results with the literature. According to the test data, potentials and challenges of electrospinning on flexible TE devices were finally discussed in this study.

Thermal warpage creates during fan-out panel level package (FOPLP) manufacturing process and it may causes challenges on subsequent procedures. To this end, finite element analysis (FEA) with element birth and death techniques were performed in this study to simulate warpages during a typical RDL-first (redistribution layer first) FOPLP process, and effective material property equations were used to simplify the complex RDL structure in an fan-out (FO) packaging. To identify the optimal factorial combinations on design parameters, Taguchi methods with adequate orthogonal array were applied on process warpage simulations. It is concluded from the results that warpage value can be reduces by 90% if the optimized experimental parameters was used for the FOPLP process.

The contact resistance of microbumps in a plastic ball grid array packaging with a through-silicon-via (TSV) structure was characterized. Accordingly, a self-designed TSV daisy-chain circuit was proposed to facilitate the formulation of the measurement paths, and the test samples were made by using a commercialized packaging process to simulate real product behaviors. Using the proposed single model and the complete model for the testing structure, about 25 $\text{m}\Omega $ was measured as the average contact resistance per microbump, and the contact resistance for each microbump was separately extracted between 4 and 60 $\text{m}\Omega $ In addition, decreasing contact resistance due to the annealing effect was observed from two different reliability tests.

Through silicon via (TSV) is the key technology used in 2.5-D and 3-D packaging. Evaluating the reliability of products using this new technology has been challenging because of complex environmental factors. The aim of this paper was to design and implement a systematic reliability experiment to test self-designed TSV samples under the combinations of several different environmental variables. The Weibull distribution model was used to extract parameters from the experimental data for the statistical evaluation of TSV reliability. After analyzing the Weibull parameters, the environmental stresses that accelerate TSV unreliability were identified and compared, and a simple empirical unreliability equation was proposed. In addition, we observed that using a power law was an effective mean on making TSV reliability curve fittings. Failure analyses by optical microscopy, scanning electron microscopy, and energy dispersive spectrometer were finally reported.

Based on our previous works, this paper proposes a new measurement methodology to extract the Seebeck coefficients for single layer, thin-film thermoelectric devices developed on different flexible substrates. With the new sandwich-like apparatus design, a stably controlled temperature gradient environment is created on the test sample, and spring type probes are employed for Seebeck coefficient extraction so that the measurements are faster and more accurate. With the experimental results on Seebeck coefficient acquirements, capability of the new apparatus was verified with reproducible data.

This paper presents the realization of a flexible thermoelectric (TE) generator as a textile fabric that converts human body heat into electrical energy for portable, low-power microelectronic products. In this study, an organic non-toxic conductive coating was used to dip rayon wipes into conductive TE fabrics so that the textile took advantage of the TE currents which were parallel to the temperature gradient. To this end, a dyed conductive cloth was first sewn into a TE unit. The TE unit was then sewn into an array to create a temperature difference between the human body and the environment for TE power harvesting. The prototype of the TE fabric consisted of 48 TE units connected by conductive wire over an area of 275 &times, 205 mm2, and the TE units were sewn on a T-shirt at the chest area. After fabrication and property tests, a Seebeck coefficient of approximately 20 &mu, V/K was measured from the TE unit, and 0.979 mV voltage was obtained from the T-shirt with TE textile fabric. Since the voltage was generated at a low temperature gradient environment, the proposed energy solution in actual fabric applications is suitable for future portable microelectronic power devices.

Through-silicon via (TSV) is one of the key technologies on three-dimensional integration packaging. In this article, an experimental methodology with circuit models was proposed for electrical characteristic tests on typical TSV structures. To this end, self-developed test patterns such as the via chains, the snake interconnections and the Kelvin structures with different dimensions were designed and manufactured. Suitable electrical measurement methodologies were next employed to characterise the element behaviours of the patterns. Based on the experimental data, electrical circuit models for the TSV structures were introduced and the parameters of the model were exacted. The validity and accuracy of the electrical model were finally verified and the TSV characteristic measurements can be performed through a simpler process.

Because of the coefficient of thermal expansion and the hygroscopic swelling mismatches on plastic packaging materials, stress and reliability issues on microelectronic packaging structures are extremely important for the packaging industry. Through the self-design test chips with the piezoresistive microstress sensors, this paper presents the experimental methodologies for stress and reliability monitoring on typical plastic ball-grid-array packaging. To this end, coefficients of the sensors are first calibrated, and stress monitoring is next performed with simultaneously thermal and hygroscopic loadings under steady-state and cyclic environments, respectively. The Weibull reliability model is next applied based on the experimental data and the parameters of the model are extracted. After real-time monitoring on stress variations during the reliability test, about 0.8 MPa of stress decrease is measured on each reliability cycle.

This paper introduces two advanced high-power diode packaging designs, respectively named Z-type and A-type from the Zowie Technology Corp., and analyzes temperature and thermo-stress distributions in the two diode packaging structure. To this end, different currents were first provided to the experiments and temperatures on diode surfaces were recorded to extract suitable thermal convective coefficients. The followed simulations were performed and the mechanical behaviors of the two packaging designs are obtained. This paper finally compared the simulation results with discussions.

As high performance MEMS devices are introducing, MEMS packaging using 3D high density packaging with Through Silicon Vias (TSV) technology becomes attractive. However, different criterions for reliability tests on TSV structures were found without consistency in the literature so that a study on criterion itself becomes necessary. To this end, this paper performed the Temperature Humidity Cycling Test (THCT) on the test samples with two different TSV structures. We next analyzed the experimental data with different failure criterions on relative resistance change to build the Weibull failure curves. After comparing the parameters extracted from the experimental data, effects on using different criterions on TSV reliability tests are discussed

Moisture is one of the major contributing factors in fracture and reliability issues for microelectronic packaging. To characterize the moisture-induced stress distribution inside the packaging structure, an in situ, quantitative, and nondestructive experimental methodology is needed. This paper proposes the use of piezoresistive sensors to measure moisture-induced stress in a plastic low profile, fine pitch, ball grid array (LFBGA) packaging. The measurements include hygroscopic swelling stress extractions and real-time stress monitoring of the popcorn phenomenon, and the results associated with gravimetric analyses are reported. Postreflow scanning acoustic microscope (SAM) inspection results and cross section observations are used as experimental verification. Comparing with thermal stresses previously measured on the same package, it is found that the hygroscopic mismatch stress is significant and important for package engineers. In addition, piezoresistive sensors were proven useful in this work for recording popcorn occurrence and monitoring the stress drops at the popcorn initiation.

This paper develops a multifunctional test chip for property extractions on packaging design. Components on this test chip include the diodes as the temperature sensors; the polysilicon units as the heaters; the piezoresistors as the stress sensors; and the pads as well as the related metal connector designs for the electrical parameter extractions. To save the sensor numbers and the connecting wires, sensors on the test chip surface were put according to structure symmetry. Since each packaging design has its individual size, components on the test chip surface were laid based on assembly of small unit cells, so that flexible test chip size can be obtained to fit the requirements from different packaging dimensions. The inductance and capacitance for the packaging leads were also extracted under microwave frequency operations, and a testing fixture was built to cooperate the Quad Flat Package (QFP) samples with the RF-RLC meter. The availability of the new measurement system designs was demonstrated from...

This paper developed a new methodology which is a sandwich-like platform to measure Seebeck coefficient for single layer thin-film thermoelectric devices which are flexible and wearable without environmental limitation. With our new apparatus, a stably controlled temperature gradient environment is created on thin-film test samples so that the commonly used and simple probing can be employed for Seebeck coefficient measurements. This paper finally verified the accuracy and availability of the new experimental design through Seebeck coefficient measurements on a typical organic conductive material (PEDOT)

This paper concentrates on the mechanical, the electrical, and the acoustical properties of the Ta–N films deposited by radio frequency (rf) magnetron reactive sputtering in Ar/N2 gas mixtures. As the nitrogen partial pressure increased, a microstructure transformation of the films from columnar polycrystalline to amorphous was observed, and the differences on the acoustic properties were measured by the picosecond ultrasonic technique. We also found that the electrical resistivities of TaNx films rose steeply by six orders of magnitude owing to the lack of extra nitrogen as the donors, and excess electron scattering caused by the porous structure.

We have performed a picosecond ultrasonic study of the effects of oxygen partial pressure on the acoustic velocity in zirconium oxide films made by radio frequency reactive sputtering. To derive more accurate and reliable values of sound velocity, various reflective layers were used to enhance the echo signals of acoustic pulses photoexcited by an ultrafast laser. It is found that the acoustic responses of the samples with a W reflective layer are much stronger than those with a Si or SiO2 reflective layer. In addition, the W reflective layer generates extra photoacoustic waves, which can be utilized to improve the accuracy of velocity measurement. The thin film velocities we measured were 10∼24% less than the bulk value, and exhibited a strong dependence on the growth conditions and the microstructure of films.

In this work, a simple assembled structure was designed and fabricated so that the calibration procedures on piezoresistive stress sensors for microelectronic packaging can be simpler, more accurate, and more efficient. After comparing with the previous work results, validity of the aforementioned new structure has been demonstrated through experimental data. Since many accessory experimental facilities employed in traditional calibrations become unnecessary, the new methodology takes great advantage on piezoresistive coefficient extractions, especially for calibration at temperature other than room temperature.

In our previous works, the piezoresistive sensors have been demonstrated to be accurate and efficient tools for stress measurements in microelectronic packaging. In this study, we first designed test chips with piezoresistive stress sensors, temperature sensors as well as heats, and the test wafers were next manufactured through commercialized IC processes. Piezoresistive sensors on silicon strips, which were cut directly from silicon wafers at a specific angle, were then calibrated, and highly consistent piezoresistive coefficients were extracted at various wafer sites so that both normal and shear stress on the test chips can be measured. Finally, we packaged the test chips into 100-pin PQFP structures with different batches and measured internal stresses on the test chips inside the packaging. After measuring packaging induced stresses as well as thermal stresses on several batches of PQFPs, it was found that the normal stress diversities were obvious from different batches of the packaging structure, and the shearing stresses were approximately zero in all of the PQFPs at different chip site.

In this paper, we perform thermal and thermo-stress analyses on diode packaging with both currently used (traditional) and the newly designed (Zowie) structures in a 5W power adapter. To this end, a global-local methodology with ANSYS FEM software were employed with the equivalent material property equations, and temperature distribution measurements were simultaneously carried out for verification and extracting boundary conditions. The simulated mechanical behaviors on the two packaging designs are finally compared with discussions in this study.

Through Silicon Via (TSV) is the key technology for the 2.5D and 3D packaging, but reliability evaluations on the new technology products are limited because of the complexity of the environmental issues. To this end, reliability experiments on self-design TSV samples under combinations of several different environmental variables were proposed and performed in this study. The Weibull distribution model was next employed for reliability analyses and the parameters for each of the experimental results were extracted. After analyzing the Weibull parameters, factors that accelerate TSV unreliability are compared with discussions. This paper finally presents failure analyses through OM/SEM observations.

Stress measurements in microelectronic packaging through piezoresistive sensors take the advantage of both in-situ and nondestructive. In this study, test chips with both p-type and n-type piezoresistive stress sensors, as well as a heat source, were first designed, then manufactured by a commercialized foundry so that the uniformity of the test chips was expected. Both temperature and stress calibrations were next performed through a special designed MQFP (Metal Quad Flat Package) and four-point bending (4PB) structure, respectively. Measurements of stresses which are produced due to both manufacturing process and thermal effects on the test chips were finally executed, and approximately linear relationships were observed between stress and temperature as well as stress and input power. It is concluded that n-type piezoresistive stress sensors are able to extract stress in microelectronic packaging with good accuracy.

Based on experimental data, a simple R–C (thermal resistance–heat capacitance) model with software precaution strategies are proposed in this paper to predict the steady-state temperature of the circuit in an electronic packaging in real time. Further developments on the new methodology lead to real time monitoring if input power and/or the environment are changing during operations. It is concluded that the new methodologies, which make the over-temperature prediction much more reliable, efficient, sensible, and faster, can be easily employed for over-temperature protection designs on electronic packaging. [S1043-7398(00)00301-7]

The equation for transversely varying thickness modes in doubly rotated quartz resonators is applied in the analysis of contoured resonators with rectangular electrodes. The influence of both the contouring and the continuity conditions at the edges of the electrodes are included in the analysis. The steady‐state forced vibrations of contoured trapped energy resonators is treated and a lumped parameter representation of the admittance, which is valid in the vicinity of a resonance, is obtained. Calculated results are presented for a number of trapped energy resonators with shallow and beveled contours.

With the assistances from iteration methodology for heat dissipation property analyses and the effective material properties for the relatively complex PCB structures, this paper extracts the thermal resistance and the transient thermo-mechanical behaviors during reflow for two compactable high power diode packaging through the ANSYS software. After the simulations, further improvements on packaging structure designs were discussed according to the temperature and stress results.

Due to the carrier mobility changes with the mechanical loading and its small size, the MOSFET (metal-oxide-semiconductor field-effective-transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging. In this work, a complete and accurate approach to calibrate the coefficients for both types of MOSFET stress sensors under thermal and mechanical loadings was investigated quantitatively. Through data from different measurement modes on different types of MOSFET, the optimal experimental methodology was next proposed for the sensor applications on packaging stress extraction. The thermomechanical coupling coefficients for the selected experimental mode were finally extracted so that packaging stress measurements with MOSFET under elevated temperature can be performed more accurately.

In order to assess the reliability behavior of a typical TSV structure, this study describes the reliability tests to qualify the samples with three types of the TSV test-keys, which includes the Kelvin structure, the via-chain, and the meander metal lines. With enough number of the samples for statistic analyses, resistances of the samples were first found increased after the preconditioning process. The temperature cycling tests (TCT) and the temperature humidity cycling tests (THTC) were next performed according to the JEDEC standards, and resistances variations on the samples were recorded during the tests. The Weibull parameters for the testing samples were finally extracted from the testing data to obtain the lifetime performance of the samples.

The MOSFET (Metal-Oxide-Semiconductor Field-Effective-Transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging because the measurements are nondestructive, in-situ, real-time, and the sensor is relatively small. To this end, this paper studies the stress behaviors of both types of the MOSFET micro stress sensors. In this work, a self-developed four-point bending (4PB) measurement methodology is employed and the stress coefficient calibrations on the MOSFET sensors were next performed. After measurements, stress coefficients for both types of the MOSFET were successfully extracted with discussions. After comparing with the previous extracted temperature coefficients on the same devices, it is also concluded that the temperature effect is extremely important for the MOSFET sensor applications.

It is well known that the CTE mismatch and the hygroscopic swelling mismatch in a plastic packaging lead reliability issues so that a suitable extraction methodology on packaging stress and failure parameters are needed. To this end, we first designed and made the piezoresistive stress sensors for packaging stress measurements and performed the sensor calibrations. Test chips were next packaged into a typical plastic packaging and the hygroscopic stress were measured. Finally, a reliability test was performed to extract the long-term effects and the reliability parameters. It is concluded from the works that the hygroscopic mismatch stress is about 50 MPa and it is significant for the packaging. It is also concluded that the Weibull reliability model is suitable for the PBGA packaging, and the Weibull parameters were successfully extracted.

The through silicon via (TSV) technology brings a key to 3D integration on wafer level packaging (WLP) by stacking chips to generate direct electrical interconnecting paths. Most of the related literatures employed the daisy chain test patterns to measure the electrical continuity and to evaluate the single via resistance. However, the single via resistance is actually the contact resistance between the two metal layers at the via bottom. In this paper, we developed new test patterns with suitable electrical measurement methodologies to evaluate several typical performance, including the contact resistance, on TSV with better accuracy.

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/°C and 0.60 MPa/°C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency, different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

Stress measurements in microelectronic packaging through the MOSFET devices have attracted great attentions because the measurement is in-situ and nondestructive. In this study, a new assembled methodology was designed and applied so that the calibration procedures on MOSFET stress sensors can be simpler and more accurate. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on linear relationships between drain current variation and the mechanical and/or thermal effects, and the results suggested that the MOSFET devices is a useful in-situ stress sensorsin electronic packaging. It is concluded that the newly experimental design and the extracted parameters are useful for MOSFET stress sensor's design and applications.

An RLC meter was used to measure the inductances and capacitances of both plastic quad flat package (PQFP) and plastic ball grid array (PBGA) with test chips inside the packages. A test chip was used to simulate the real package condition, although the standard measurement guideline such as EIA/JED123 does not include it. Combining test chip layout, test ground fixture and grounding technique, the complex n-lead model could be simplified into a one-lead model which leads to obtain the inductance or capacitance of pins in a package easily. Two kinds of packages PQFP and PBGA were investigated, each one had five samples which were measured from 0 to 3 GHz range. From the inductance/ capacitance versus frequency curves, the frequency limitation of packages is obtained. The average inductance values per mm for both PQFP and PBGA are 0.99plusmn0.05 nH/mm and 0.95plusmn0.05 nH/mm, respectively, while the average capacitance values for PQFP and PBGA are 0.89plusmn0.02 pF and 0.79plusmn0.02 pF as relating to each.

In this work, we studied the availability of p-type MOSFET with 1 mum channel width and 0.15 mum channel length as a stress sensor. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on a new measurement methodology, and linear relationships between drain current variation and stress and/or thermal effects were obtained. According to the measurement data, the extremely important thermal effect was also noted. It is concluded in this work that the newly experimental design and the extracted parameters are useful for MOSFET stress sensor's design and applications.

The purpose of this paper is to study the MOSFET stress sensor behaviors and to develop the related measurement methodology. With the newly developed technology, the piezoresistance coefficients of the MOSFET were extracted, and the strain and temperature effect induced MOSFET characteristics were obtained. The results of this study can be used to adjust the chip structure in a packaging so that the optimal packaging technology and material can be chosen, and accuracies of the numerical analysis can be verified through experimental data with the new technology studied in this paper.

We compared the RF behaviors on a typical plastic packaging (100-lead PQFP) due to molding compound effects in this study. To this end, a testing fixture was first designed to cooperate the measurement on an Agilent 4287A RLC meter. The PQFP samples, both with and without molding compounds, were prepared afterward. Inductances and capacitances on the leads of the testing samples under microwave frequency operations were next measured and compared, respectively. It is concluded from the first measurements that the molding compound in a packaging will raise the capacitance values but it will not affect to the inductance of a packaging lead to bond wire under RF frequency.

In this paper, we developed a multifunctional test chip for property extractions on packaging design. Components in this test chip include diodes as the temperature sensor; polysilicon units as the heater; piezoresistors as the stress sensor; and pads as well as the related metal connector designs for electrical parameter extractions. To save sensor numbers and connecting wires, sensors on the test chip surface were put according to structure symmetry. Since different microelectronic packaging has individual size, components on test chip surface were laid based on assembly of small unit cells so that the flexible test chip size can be employed to fit requirements from different packaging dimensions. Besides, we considered the inductance/capacitance extractions of packages for high frequency condition. A test structure was finally designed to cooperate the QFP packages for the RLC measurement, and the availability of the designed was demonstrated from testing data.

In acoustic devices such as film bulk acoustic resonators (FBAR), it is most essential to accurately determine the thin-film sound velocities in situ. In this work, we analyzed the microstructure properties of the zirconia thin films deposited by RF magnetron reactive sputtering with various oxygen partial pressures, and measured the longitudinal film velocity with picosecond ultrasonic technique. The picosecond ultrasonic waves were produced by irradiating the testing samples with an ultrafast laser pulse generated by a self-made mode-locked Ti: Sapphire laser, and detected by a delayed probe laser pulse. The acoustic velocities of the thin films were next determined from the echo times of the ultrasonic waves. To derive more accurate and reliable velocity, three different reflective layers were employed so that the echo shapes and intensities of ultrasonic wave can be compared. It was found in this work that the thin film velocities we measured were less than the bulk value, which can be calculated from Young's modulus and the density. Meanwhile, with the measurement results, it is also found that the measured acoustic velocity and the microstructure of films have strong dependence on the growth conditions. Consequently, accurate thin film velocity will be obtained for an SMR designer through better controlling on deposition conditions during manufacturing process.

Piezoresistive sensor has been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, square test chips with four piezoresistive stress sensors and the accompanied diode temperature sensors have been first designed, fabricated and calibrated. A heater was also laid at the chip center. We next packaged test chips into 196-ball LFBGA (Low profile, Fine pitch BGA) packaging and measured stresses on chip surfaces inside the packaging. After measuring the packaging-induced stresses as well as stresses under constant environment temperatures, it was found that compressive stresses were obtained at room temperature, and the compressive stresses are relaxed as temperature increases. It was also found in the same experiments that the average slopes of the temperature-stress curves are between 0.45 Mpa//spl deg/C/spl sim/0.65 Mpa//spl deg/C, and localized stress distributions are observed. For thermal stress experiments, temperatures on chip surfaces at different power levels were first derived. Compressive chip stresses were next measured and the stresses then become tension as the chip power increased. Since all of the measured stresses are much less than the yielding stress, it is concluded that chips inside 196-ball LFBGA packaging will not failure due to thermomechanical effects during regular operations.

The equation for transversely varying thickness modes in doubly-rotated quartz resonators is applied in the analysis of contoured resonators with rectangular electrodes. The influence of both the contouring and the continuity conditions at the edges of the electrodes are included in the analysis. The steady-state forced vibrations of contoured trapped energy resonators is treated and a lumped parameter representation of the admittance, which is valid in the vicinity of a resonance, is obtained. Calculated results are presented for a number of trapped energy resonators with shallow contours. >

Recent work on the determination of optimal orientations and aspect ratios of SC-cut quartz resonators stiffened by rectangular quartz plates has shown that the influence of fabrication imperfections is minimized when two clips of reasonable size are used on each of the large sides. In this work existing computer programs are used in the calculation of the influence of the spacing between the two clips and the stiffnesses of the clips on the sensitivity to fabrication imperfections in order to find optimal conditions. Both contoured and flat plate trapped energy are treated. The smaller dimension of the support rectangle is determined by a criterion associated with the energy in the mode shape for each particular harmonic. A summary of recommendations based on all the calculations is presented. >

In this work, a simple assembled structure was designed and fabricated so that the calibration procedures on piezoresisitve stress sensors for microelectronic packaging can be simpler, more accurate, and more efficient. After comparing with the previous work results, validity of the aforementioned new structure was next demonstrated through experimental data. Since many accessory experimental facilities employed in traditional calibration procedure become unnecessary, the new methodology takes great advantage on piezoresisitve coefficient calibrations, especially for calibration at temperature other than room temperature.

We report a double-transducer technique for more effective generation of picosecond acoustic waves. A tungsten layer, which is buried under a transparent film and a thin top metal transducer, plays the role of a bottom laser-acoustic transducer as well as a high-impedance acoustic reflector. The pulse shape and the induced piezoreflectance response of the acoustic wave launched by the bottom transducer are different from the conventional top transducer. The effect of the bottom transducer depends on the thicknesses and optical constants of the top transducer and the transparent film. The accuracy of velocity measurement can be raised owing to more efficient energy utilization, halved pulse broadening and attenuation of the tungsten-launched waves, and the added signatures on the reflectance curve.