42 results on '"Vandeweyer, T."'
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2. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
3. Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell
4. Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density
5. Advanced Cu interconnects using air gaps
6. In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers
7. In-line metrology for characterization and control of extreme wafer thinning of bonded wafers
8. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application
9. A 400GHz fMAX fully self-aligned SiGe:C HBT architecture
10. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to lOnm and 30nm gate length
11. A new complementary hetero-junction vertical Tunnel-FET integration scheme
12. Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry
13. Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application
14. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation
15. Investigation of Forming and Its Controllability in Novel HfO2-Based 1T1R 40nm-Crossbar RRAM Cells
16. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
17. Record low contact resistivity to n-type Ge for CMOS and memory applications
18. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout
19. Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell
20. Immersion lithography and double patterning in advanced microelectronics
21. A 400GHz fMAX fully self-aligned SiGe:C HBT architecture
22. Redevelopment of the Schoonebeek Oil Field, Netherlands – Tackling a Giant with the Necessary Detail
23. High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants
24. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
25. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
26. A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process
27. Gatestacks for scalable high-performance FinFETs
28. A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
29. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography
30. Spacer defined FinFET: Active area patterning of sub-20nm fins with high density
31. Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency
32. Investigation of New Slection Citeria for an Otimized Imersion Process
33. Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology.
34. Comprehensive approach to MuGFET metrology.
35. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques.
36. Air gap integration for the 45nm node and beyond.
37. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application.
38. Air gap integration for the 45nm node and beyond
39. A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
40. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout.
41. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation.
42. In-line metrology for characterization and control of extreme wafer thinning of bonded wafers.
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