High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout.

Details

Language :

English

ISBNs :

9781424454518

Database :

Complementary Index

Journal :

2010 Symposium on VLSI Technology (VLSIT)

Publication Type :

Conference

Accession number :

81513457

Full Text :

https://doi.org/10.1109/VLSIT.2010.5556133