Search

The development of a self-consistent electrothermal transport model that coupled electrical and thermal transport equations and which could be applied to AlGaN/GaN device structures grown on the three different substrate materials such as SiC, Si, and sapphire is reported. The marked difference observed in the saturated current levels for AlGaN/GaN structures on SiC, Si, and sapphire substrates is directly related to the different self-heating levels that resulted from the different biasing conditions and the distinctive materials.

The article studies 4H-SiC {0001} p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with deposited Si[O.sub.2] followed by [N.sub.2]O annealing. Findings suggest that the deposited oxides annealed in [N.sub.2]O are efficient in improving the performance of 4H-SiC p-channel MOSFETs.

Several experimental and computational studies are conducted to determine the forward current density ([J.sub.F])-forward voltage ([V.sub.F]) characteristics of 4H-silicon junction barrier Schottky (JBS) diodes. These characteristics are shown to be highly affected by the lateral spreading of the implanted aluminum ions and implantation-induced defects.

A band-offset-based unified-RAM (URAM) cell fabricated on a Si/[Si.sub.1-y][C.sub.y] substrate is used for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. The band-engineered URAM has yielded a cost-effective process that is compatible with a conventional body-tied FinFET SONOS and the URAM has shown highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.

A large-area, 250 [micro]M-diameter, 4H-SiC avalanche photodiodes with low dark current and high gain is described. The differential resistance of the recessed-window device at zero bias is estimated and a record high specific detectivity is achieved due to high external quantum efficiency, large area, and large differential resistance.

The junction temperatures, thermal stabilities, and thermal runaway effects of self-heating unipolar SiC power devices are analyzed. The results showed that the risk of thermal runaway could limit the usable junction temperature of SiC devices to substantially lower than 200 degree Celsius, regardless of the device size and cooling method used.

Low-temperature MOS-gated Hall measurements and gated diode capacitance-voltage (C-V) measurements are used for characterizing both trap density and Hall mobility on 4H-silicon carbide MOSFETs with gate oxides grown by sodium enhanced oxidation (SEO) and thermally grown in [N.sub.2]O. The temperature-dependent Hall mobility measurements have revealed that inversion layer mobility in both the SEO and baseline samples are limited by Coulomb scattering from interface trapped charge and surface roughness.

The fabrication of an ac thin-film light-emitting diodes (TFWLEDs) with a hydrogenated intrinsic amorphous carbon (i-a-C:H) film as the luminescent layer and a composition-graded (CG) hydrogenated intrinsic amorphous silicon carbide (i-a-SiC:H) film as the carrier-injection layers is reported. The i-a-C:H TFWLEDs could operate under dc and ac modes and could find potential application as a candidate for light source in the future.

The effectiveness of in situ doping high-substitutional-carbon SiC:P source/drain (S/D) stressors in increasing the strain-induced ([I.sub.Dsat]) for -oriented (110)-sidewall DG FinFETs is examined. The studies have shown that a significant 20% strain-induced enhancement is seen in SiC:P S/D FinFETs, incorporating a substitutional carbon concentration of 2.1%.

The effect of different gate oxide processes on the performance of 4H-SiC MOSFETs is analyzed. Various MOS device parameters, including threshold voltage, subthreshold slope, field-effect electron mobility, sheet electron carrier concentration and Hall mobility, are correlated with different process steps.

Charge-pumping measurements are used for studying the 4H-SiC MOSFETs and the distorted shape of the charge-pumping curves. The distortion of the charge-pumping curves has occurred due to the geometric component and the acceptor-like interface states and these two effects are large in the unannealed n-channel 4H-SiC MOSFETs with low channel mobility.

The behavior of top-gated transistors fabricated by using carbon, especially epitaxial graphene on SiC, as the active material is described. The graphene devices have featured high-[kappa] dielectric and these micrometer-scale devices have negligible band gaps and hence large leakage currents.

A new method is developed for modeling and characterizing the transient response of 4H-SiC MOSFETs. The observations of trap dynamics have shown that improvements in long-term device stability are achieved by reducing oxide traps, whereas short-term stability is improved by the reduction of interface traps.

Si[N.sub.x]/Si[O.sub.2] stack-gate structures, followed by [N.sub.2]O annealing, are examined to improve the 4H-SiC metal-insulator-semiconductor (MIS) interface quality. The fabricated MISFETs with Si[N.sub.x]/Si[O.sub.2] stack-gate structure annealed in [N.sub.2]O has shown high channel mobility on the Si and C face.

A 4H-SiC single-photon avalanche diode (SPAD) operating at ultraviolet (UV) wavelengths of 280 and 350 nm is described. The combination of high single-photon detection efficiency (SPDE) and high photon count rate, low dark current rate (DCR) and low dark current have shown the emergence of the SiC SPAD as a powerful competitor in the area of UV single-photon detectors.

N-channel planar [Al.sub.2][O.sub.3]/Si[O.sub.2]/SiC MOSFETs are fabricated and the effect of a Si[O.sub.2] layer inserted between [Al.sub.2][O.sub.3] and SiC is examined. The results have shown that the interface property of the ultrathin Si[O.sub.2]/SiC structure is very good, but the interface property has degraded when the Si[O.sub.2] thickness is larger than 2 nm due to interfacial layer formation.

A comprehensive physical model is developed for the analysis, characterization and design of 4H-SiC MOSFETs. The simulator has indicated that reducing the band-edge interface trap density by a factor of ten has yielded a substantial improvement in drain current at all bias voltages and temperatures.

Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown Si[O.sub.2] and NO-annealed gate oxides are analyzed by using fast I-V measurements. Postoxidation annealing in NO has passivated the oxide traps and has reduced the instability.

N-channel enhancement MOSFETs and MOS capacitors are fabricated on 4H-SiC by using gate oxide processes based on N ion implantation and reduced thermal-budget wet oxidation. The studies have shown that N ion implantation before the gate oxidation is a suitable way to reduce the density of the Si[O.sub.2]/SiC interface states responsible of the channel conductivity decrease in the n-MOSFET.

A Monte Carlo model is developed for ion implantation in crystalline SiC, which is applied to arbitrary polytype. The studies have shown that a semiempirical electronic stopping power model is effective in simulating the dopant profiles in both channeling and random direction implants, despite its highly anisotropic crystal structure of SiC.

Hole and mixed multiplication characteristics are obtained on thick 4H-SiC avalanche photodiodes (APDs) with nominal avalanche widths between 2.7 and 6 [micro]m. Ionization coefficients are parameterized over the electric field range from 0.9 to 5 MV/cm, which have helped in the accurate prediction of the multiplication and breakdown characteristics of 4H-SiC.

The first monolithic bipolar transistor-transistor logic (TTL) integrated circuits in 4H-SiC are described. The results have shown that the SiC bipolar integrated circuits are excellent candidates for high-temperature applications.

The performance of 4H-SiC planar junction barrier Schottky (JBS) rectifiers and lateral channel JBS (LC-JBS) rectifiers is described. The lateral channel JBS rectifier is designed and demonstrated in 4H-SiC with up to 1.5-kV blocking capability and pinlike reverse characteristics.

The electronic transport in ballistic and diffusive 3C-SiC nanowire field-effect transistors (NWFETs) are examined by using a homemade 3-dimensional (3-D) quantum-mechanical simulation code and a commercial tool. In the ballistic regime, devices with undoped SiC NWs have displayed superior theoretical performances based on their simulated characteristics.

A new analytical model is developed for superjunctions devices in 4H:SiC. The model has provided valuable guidelines for the development of superjunction devices on 4H-SiC.