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The main challenge in ferroelectric (FE) random access memory (FRAM) scaling is to maintain a high polarization density on the vertical sidewall of 3-D FE capacitors. Two simple and effective methods—stress engineering and optimized interface orientation—are proposed to facilitate the preferential transition from the tetragonal to the orthorhombic phase for ferroelectricity. Four FE phase-progressive experiments were conducted for 2-D/3-D FRAMs with external stress sources and an interfacial layer (IL). Both 2-D and 3-D FRAMs show the wake-up free feature with the presence of both the external stressor and the optimized IL. To extract the sidewall polarization of 3-D FRAM, a set of testkeys was designed and studied. The 3-D FRAM shows an initial sidewall with good reliability and durability with ${P} _{r} = {18}\,\,\mu \text{C}$ /cm2 and endurance of up to 109 cycles. Furthermore, the retention test with the read mode of ${P} _{\text {0,switch}}$ and ${P} _{\text {1,switch}}$ at 85 °C was investigated, and the imprint effect was proved to be the main cause of retention loss.

This article presents the design, characterization, and modeling for the novel 3-D transformer structures based on the in-house developed 3-D integrated circuit (3-D IC) via-last backside-through-silicon via (TSV) interposer process. Differing from the conventional 2-D planar structure, the 3-D TSV design allows achieving a fully symmetric transformer with a compact size. The equivalent circuit model parameters are extracted based on the S-parameters to investigate the design tradeoff. With an inner diameter of $40~\mu \text{m}$ in the 3-D 1:1 transformer, the measured inductances of the primary and second coils are 439 and 482 pH with the $Q$ factors of 4.59 and 5.11, respectively, and the coupling coefficient is 0.136.

In this work, we successfully fabricated AlGaN/GaN HEMT on 8-inch GaN-on-Si wafer utilizing CMOS BEOL compatible process, and demonstrate an AlGaN/GaN HEMT with L g = 250nm reaching f t /f max = 50/44 GHz. By semi-automatic RF measurements mapping in complete 8-inch wafer area, results exhibit average f t = 48GHz with NU = 7.6% and average f max = 42GHz with NU = 5%, revealing the outstanding uniformity of 8-inch standard CMOS manufacturing tools.

Ferroelectric tunnel junction (FTJ) with ultrathin 3 nm-thick Hf 0.5 Zr 0.5 O 2 (HZO) is investigated. The high current density up to 100 A/cm2 is at least 10 times higher than that in previously reported HZO FTJs. It is suitable for future nanoscale FTJ with a GΩ cell resistance for the application of in-memory computing. The insertion of a thin Al 2 O 3 interfacial layer is found critical to alter the switching polarity and increase current density.

Dopamine detection is investigated by using annealed platinum membrane on Ti/n-Si substrate for the first time. Oxidation/reduction peaks with and without dopamine in pH7 solution measured by cyclic-voltammetry (CV) are observed clearly. The sensor shows repeatable and stable CV curves. The oxidation/reduction peak currents increase with increasing scan rate. The peak current increases with increasing pH value. Dopamine with a low concentration of 1 μM and small sample volume of 10 μL is detected in current-time measurement within the short time of 5 s.

The Tunnel Magnetoresistance (TMR) biosensor with different magnetic tunnel junction (MTJ) aspect ratios was developed. With the specific designs and the process development, the sensing distance of the active sensor could be shortened to 74.2 nm to obtain larger magnetic bead (MB) induced signal and the reference sensor, whose sensing distance was 350 nm thicker than that of the active sensor, was used as the baseline during the detection to eliminate the environment noise. The simulation method which could well characterize the TMR element was also developed. Finally, the experimental results of the MB detection was shown. W1/L8 MTJ structure, whose resistance was $40 \mathrm{k}\Omega$, had the highest sensitivity $(0.444 \Omega /$MB). Overall, according to the various designs of the MTJ structures, the TMR biosensor with low environmental interference and high sensitivity could be used in variety of the in-vitro diagnosis of Point of Care (PoC) applications in future.

Dopamine sensing using a simple Pt/n-Si structure is investigated for the first time. Polycrystalline Pt membrane with a thickness of 3 nm in Pt/n-Si structure is observed by high-resolution transmission electron microscope image. This Pt/n-Si structure shows a good pH sensitivity of 0.58/pH by measuring current-time response at pH values from 2 to 10. Repeatable and stable sensing of dopamine with a low concentration of 10 pM are obtained. Dopamine with long concentration range of 10 pM to 1 μM is measured and the sensing mechanism is due to Schottky barrier height modulation through reduction-oxidation of Pt membrane in contact of dopamine. This study is useful for future early diagnosis of Parkinson's disease.

Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.

In this paper, the optimization of Cu chemical-mechanical polishing (CMP) performance (dishing) for the removal of thick Cu-plating overburden due to Cu plating for deep through silicon via (TSV) in a 300-mm wafer is investigated. Moreover, backside isolation oxide CMP for TSV Cu exposure is examined. To obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu-polishing process. First, a bulk of Cu is removed with the slurry of high Cu removal rate and second, the Cu surface is planarized with the slurry of high Cu passivation capability. The Cu dishing can be improved up to 97% for the 10-μm-diameter TSVs on a 300-mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly optimized Cu-plating overburden for TSVs and redistribution layers. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a larger TSV diameter still keep in a plateau-like shape after CMP.

In this work, we utilize a photo-chemical etching (PCE) method to form through-glass-via (TGV). The PCE is a low cost, damage-free and potentially large-area method for TGV formation. An ultra-violet (355 nm) pulse laser was used to illuminate the glass surface. The illuminated region will crystallize after thermal annealing in a furnace. The crystallized glass shows much faster etching rate than the amorphous region in HF solution. For a relatively thick (600 nm) glass, a via-hole with diameter of around 60 μm was demonstrated in laser energy of 11 J/cm2. No laser damages were observed. In comparison, at least 10 times higher energy was required to drill a glass directly. Micro-cracks were form around the glass-via. In addition, a 40 selectivity was achieved to the crystallized and amorphous region. This simple and useful method paves a straight road for 3-D integration.

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.

The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer (28mm × 28mm) with double sided wiring layers. This interposer is used to support a very large chip (22mm × 18mm) on its top-side and 2 smaller chips (10mm × 10mm) at its bottom-side (a truly 3D IC integration). The bottom side of this interposer is attached to an organic substrate (40mm × 40mm) (with ordinary lead-free solder bumps). The lead-free micro solder bumps (Cu/Sn) on all the chips are made by wafer bumping with a UBM (under bump metallurgy) of Ti/Cu and the bump structure of Cu and Sn.

In this study, thin wafer handling of 300mm wafer for 3D IC Integration is investigated. Emphasis is placed on the determination of the effect of a dicing tape on thin-wafer handling of wafers with Cu-Au pads, Cu-Ni-Au UBM, and TSV interposer with RDL. Also, thin-wafer handling critical issues such as the chip/interposer wafer, carrier wafer, temporary bonding, thinning, backside process, de-bonding, and assembly are presented and their potential solutions are discussed. Finally, state-of-the-art of materials and equipments for thin-wafer handling are examined.

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 μS, and high Ion/Ioff ratio of 106 can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.

For the first time, modification of Si doping in Hf-silicates with respect to thermal budget is investigated. Tetragonal phase of HfO2 in Hf-silicate leads to higher dielectric constant after a critical point of thermal budget. Lower critical point (lower thermal budget) is needed for Hf-silicate with a lower Si doping. The tetragonal phase induced higher dielectric constant tends to remain constant even with longer annealing time while the leakage current tends to increase. The optimum condition is a trade-off between the pro of tetragonal phase and the con of the leakage current.

Operation properties of polysilicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile semiconductor memory (NVM) devices with stacked tunneling and charge trapping layers were investigated in this work. Clear enhancement on operation speed and satisfactory retention of NVM device were achieved by adopting stacked tunneling oxide. Enhancement on programming speed but degradation on erasing operation was observed for device with stacked charge trapping layer. Finally, operating characteristics of devices with stacked tunneling oxide, stacked charge trapping layer, and combining both stacked tunneling oxide and charge trapping layer were compared and discussed.

The etch rate of HfO2 etch processing has been feedback controlled in inductively coupled Cl2/N2/Ar plasmas. The ion current and the root mean square rf voltage on the wafer stage, which are measured using a commercial impedance meter connected to the wafer stage, are chosen as controlled variables because the positive-ion flux and ion energy incident upon the wafer surface are the key factors that determine the etch rate. Two 13.56 MHz rf generators are used to adjust the inductively coupled plasma power and bias power which control ion density and ion energy, respectively. The adopted HfO2 etch processing used rather low rf voltage. The ion-current value obtained by the power/voltage method is underestimated, so the neural-network model was developed to assist estimating the correct ion-current value. The experimental results show that the etch-rate variation of the closed-loop control is smaller than that of the open-loop control. However, the first wafer effect cannot be eliminated using closed-loop c...

In this study, the characteristics of Ta/chemical SiO2/Si devices with their chemical oxides formed by various chemicals, including HNO3, SC1, and H2SO4+H2O2 solutions, were first investigated. We found the HNO3 split depicts the lowest leakage current and the best hysteresis behavior. Next, chemical oxide formed by HNO3 was applied to form the interfacial SiO2 layer for metal–oxide–semiconductor (MOS) devices with Ta/HfAlO/chemical SiO2/Si structrue. The effects of a high-temperature spike anneal were then studied. We found that the spike-anneal process can effectively reduce the thickness of the chemical oxide from 10 to 7 A, thus is beneficial in preserving the low effective oxide thickness (EOT) of the structure. Furthermore, both the gate leakage current and stress-induced leakage current (SILC) were also effectively suppressed by the high-temperature spike-anneal.

Memory characteristics of the high-κ HfO2/TiO2/Al2O3 single quantum well in a p-Si/Al2O3/HfO2/TiO2/Al2O3/platinum capacitor structure have been investigated. All high-κ films have been deposited by atomic layer deposition. A significant memory window of ~1.6 V at a low gate voltage operation of 2 V, a high charge storage density of ~3.6×1012/cm2, a moderate leakage current density of 1×10-6/cm2 at a gate voltage of -2 V, and a negligible charge loss of

The etch selectivity of HfO2 to Si reported to date is poor. To improve the selectivity, one needs to either increase the etch rate of HfO2 or decrease the etch rate of Si. In this work, the authors investigate the etch selectivity of HfO2 in Cl2∕N2 plasmas. In particular, the effects of in situ N2 plasma treatment of HfO2 and Si were investigated. The silicon substrate was exposed to nitrogen plasma and was nitrided, which was confirmed by x-ray photoelectron spectroscopy. The nitrided Si etching was suppressed in Cl2∕N2 plasmas. The effectiveness of nitridation was studied with varying the plasma power, bias power, pressure, and N2 plasma exposure time. The results show that the etch resistance increased with increased power and decreased pressure. A minimum exposure time was required to obtain etch resistant property. The applied bias power increased the etch rate of Si substrate, so it should not be used during N2 plasma treatment. Fortunately, the etch rate of HfO2 was increased by the nitridation pr...

Nonstoichiometric hafnium oxide (HfOx) resistive-switching memory devices with low-power operation have been demonstrated. Polycrystalline HfOx (O:Hf=1.5:1) films with a thickness of 20 nm are grown on a titanium nitride (TiN) bottom electrode by commercial atomic layer deposition. Platinum (Pt) as a top electrode is used in the memory device. Voltage-induced resistance switching is repeatedly observed in the Pt/HfOx/TiN/Si memory device with resistance ratio is greater than 10. During the switching cycles, the power consumptions for high- and low-resistance states are found to be 0.25 and 0.15 mW, respectively. At 85 °C, the memory device shows stable resistance switching and superior data retention with resistance ratio is greater than 100. In addition, our memory device shows little area dependence of resistance-switching behavior. The anodic electrode containing noble metal Pt serves an important role in maintaining stable resistance switching. The resistance switching in the HfOx films is thought to be due to the defects that are generated by the applied bias. The nonstoichiometric HfOx films are responsible for the low SET and RESET currents during switching. Our study shows that the HfOx resistive-switching memory is a promising candidate for next-generation nonvolatile memory device applications.

TiO2 nanocrystals were successfully fabricated using an atomic-layer-deposition (ALD) system. A TiN/Al2O3-laminated structure was employed as a starting structure, and after appropriate annealing, TiN was oxidized and TiO2 nanocrystals were formed. Experimental results indicate that rapid thermal annealing (RTA) temperature and annealing time are very critical factors. Also, the thickness of each TiN layer in the TiN/Al2O3-laminated starting structure is critical for TiO2 nanocrystal formation. Capacitance–voltage (C–V) measurement evidenced that an optimal annealing condition exists and an optimal annealing temperature and annealing time mainly depend on the thickness of each TiN layer in the TiN/Al2O3-laminated starting structure.

A high-κ HfO2/HfAlO/HfO2 nanolaminate charge trapping layer in a p-Si/SiO2/[HfO2/HfAlO/HfO2 nanolaminate]/Al2O3/platinum memory capacitor has been investigated. High-κ HfO2, Al2O3, and HfO2/HfAlO/HfO2 nanolaminate charge trapping layers are deposited by atomic layer deposition. Well-behaved counter clockwise capacitance–voltage hysteresis characteristics are observed for all memory capacitors. A large memory window of ~10 V, a very low leakage current density of ~5×10-9 A/cm2 at a gate voltage of -5 V, a high charge trapping density of ~1.6×1013/cm2, and a low charge loss of ~20% after 10 years of retention for the HfO2/HfAlO/HfO2 nanolaminate charge trapping layer are observed as compared with those of pure HfO2 and pure Al2O3 charge trapping layers. Excellent memory characteristics of HfO2/HfAlO/HfO2 nanolaminate layers are obtained owing to the layer-by-layer charge storage. High-κ HfO2/HfAlO/HfO2 nanolaminate charge trapping layers can be used in future nanoscaled high-performance nonvolatile memory device applications.

The physical properties of HfO2 and Hf-silicate layers grown by the atomic layer chemical vapor deposition are characterized as a function of the Hf concentration and the annealing temperature. The peaks of Fourier transform infrared spectra at 960, 900, and 820 cm-1 originate from Hf-O-Si chemical bonds, revealing that a Hf-silicate interfacial layer began to form at the HfO2/SiO 2 interface after post deposition annealing process at 600 degC for 1 min. Moreover, the intensity of the peak at 750 cm-1 can indicate the degree of crystallization of HfO2. The formed Hf-silicate layer between HfO2 and SiO2 is also confirmed by X-ray photoelectron spectroscopy

Two integrated passive device (IPD) structures are proposed in this paper. The first structure is a differential symmetrical through-silicon via (TSV) monolithic transformer that exhibited optimal symmetry between the two ends of the primary and secondary coils, enabling the operation of a differential circuit. The second structure is a fully 3-D symmetrical TSV monolithic transformer that differs from 3-D TSV transformers proposed in the literature. In addition to the optimal symmetry between the two ends of the primary and secondary coils, the primary and secondary coils also exhibited optimal symmetry. In this study, test keys with 1∶2 and 1∶3 transformer turns ratios were applied to the structure of a differential symmetrical transformer. The fully 3-D symmetrical TSV monolithic structure was designed as a test key with a true 1∶1 turns ratio. The TSV of all test keys exhibited a 5 µm diameter, 60 µm depth, and 20 µm pitch. These test keys were simulated using HFSS, a fully 3-D simulator, and fabricated on a 300 mm wafer by using the ITRI's 3-D integrated circuit back-end-of-line process. The simulation results indicated that the inductance of the primary and second coils was 514 and 520 pH, respectively. The coils exhibited a Q factor of 12.08 and 11.98, respectively, when operated at 15 GHz, and the relative difference between the two coils was 1.15%. Compared with transformer structures proposed in the literature, the structure proposed in the present study exhibited superior symmetry between the primary and secondary coils.

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

Low-cost 3DIC process approaches are investigated in terms of 3D stacking method and TSV process integration scheme. The permanent and bumpless wafer-to-wafer (PBWW) bonding technology can be applied to the DRAM wafers in the wide-I/O memory cube application. Backside TSV process with its electrical characteristics is also studied. The combination of these two process technologies can further lower the overall process cost and speed up the mass production.

The rougher surface and raised-hollow holes were observed in the TiN/Al2O3/HfO2/Al2O3/TiN/SiO2/Si multi-stack metal–insulator–metal (MIM) capacitor sample after 1000 °C, 60 s rapid thermal annealing (RTA) process in N2. The surface became rougher partially resulted from the nucleation of TiN layer after RTA. Experimental results also indicated that the oxygen content in the HfO2 was desorbed and the remaining Hf was crystallized. Also, the TiN and Al2O3 layers were intermixed and partially re-crystallized at this high temperature. Very clear morie fringes could be observed in the high-resolution transmission electron microscopy (HR-TEM) micrographs. Also, the energy dispersive spectroscopy (EDS) results indicated that the nitrogen in TiN was desorbed and the TiN was phase transformed to TiO2. This phenomenon might result from the TiN oxidation process during the high-temperature thermal annealing.

The physical and reliability characteristics of strained-Si/sub 0.8/Ge/sub 0.2/ MOS capacitor and strained-Si/sub 0.7/Ge/sub 0.3/ MOSFET with Hf-based gate dielectrics prepared by atomic layer chemical vapor deposition are investigated. The thickness and composition of the gate dielectrics are measured by high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy, respectively. The gate leakage current and interface traps of HfO/sub 2//Si/sub 1-x/Ge/sub x/ gate structure are slightly higher as compared to the HfO/sub 2//Si MOS devices, which is basically caused by the Ge at the interface. The electrical properties of both HfO/sub 2//Si and HfO/sub 2//Si/sub 1-x/Ge/sub x/ devices can be improved with increasing PDA temperature up to 800/spl deg/C, which is due to the thicker interfacial layer grown at the interface, even though crystallization also grows with increasing temperature. However, with higher PDA temperature (>800/spl deg/C), serious crystallization of HfO/sub 2/ film causes more bulk traps induced electrical degradation. The electrical stress induced degradation of Si/sub 1-x/Ge/sub x/ substrate is slightly higher as compared to the control Si, due to more traps generations at the HfO/sub 2//Si/sub 1-x/Ge/sub x/ interface. For MOSFET, strained-Si/sub 1-x/Ge/sub x/ can effectively improve the drain current for about 20% at saturation and 69% at linear region. The higher gate leakage (J/sub g//spl sim/1.4/spl times/10/sup -9/A/cm/sup 2/ at 2 V) and lower breakdown voltage (BD/spl sim/3.1 V) of Si/sub 0.7/Ge/sub 0.3/ pMOS devices are observed as compared to control Si devices (J/sub g//spl sim/7.9/spl times/10/sup -12/A/cm/sup 2/ at 2 V and BD/spl sim/7.4 V). After the electrical stress, the degradation of drain current and transconductance and the shift of threshold voltage for Si/sub 1-x/Ge/sub x/ PMOSFET are larger than those for control Si devices, implying Ge induced trap generation at the Hf-silicate/Si/sub 1-x/Ge/sub x/ interface.

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si/sub 3/N/sub 4/ and Ta/sub 2/O/sub 5/ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si/sub 3/N/sub 4/ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta/sub 2/O/sub 5/ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta/sub 2/O/sub 5/ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta/sub 2/O/sub 5/ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to less than 5 µm for light detection from the backside. After thinning process, the backside is permanently bonded to a 500μm-thick glass carrier substrate with a transparent thermal set bonding material. After thinning, the total thickness variation of 1μm is obtained because the thermal plastic material flow during bonding process resulted in excellent thickness uniformity. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. In the assembly process of CMOS image sensor stack, firstly the analog-to-digital conversion chip was stacked onto the image signal processor chip by thermal compression bonding. Optimized bonding conditions of 250 ℃/5 sec under the bonding force of 13N were chosen and determined. Subsequently, after the stack of analogto-digital conversion chip onto the image signal processor chip, the CMOS image sensor chip was bonded onto the image signal processor/analog-to-digital conversion stack. To connect all the solder bumps between CMOS image sensor and analog-to-digital conversion chip, the higher bonding force of 18N was selected. Joined-well solder joints between these two chips could be achieved. Finally, the stacked CMOS image sensor module was attached to a print circuit board by adhesive material and wire bonding was conducted to finish the electrical connectivity between CMOS image sensor stack and print circuit board.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500µm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 µm after thinning and the total thickness variation is around 1 µm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.

Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3DIC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.

A forming-free 3-nm-thick HfOx, resistive memory device is demonstrated. The percolation threshold of insulatingto-conductive transition in the ultrathin HfOx, can be lowered by using the Ti capping layer with an adequate post metal annealing. By the reaction between Ti and HfOx,, oxygen ions are depleted from the oxide, and conductive percolative paths, which consist of charged oxygen vacancies, are formed. Without any forming step, the memory can operate with stable bipolar resistance switching by initial positive or negative voltage sweep. Possible scenarios of switching mechanism for the initial state of the device with different sweep directions are proposed. This forming-free device also exhibits an on/off ratio of about ten and excellent memory performances, including high speed (~10 ns), low operation voltages ( 106 cycles), good nonvolatile property (500 min at 85 °C), and 2-b switching per cell.

The memory performance of hafnium oxide (HfOx)-based resistive memory containing a thin reactive Ti buffer layer can be greatly improved. Due to the excellent ability of Ti to absorb oxygen atoms from the HfOx film after post-metal annealing, a large amount of oxygen vacancies are left in the HfOx layer of the TiN/Ti/HfOx/TiN stacked layer. These oxygen vacancies are crucial to make a memory device with a stable bipolar resistive switching behavior. Aside from the benefits of low operation power and large on/off ratio (>100), this memory also exhibits reliable switching endurance (>106 cycles), robust resistance states (200°C), high device yield (~100%), and fast switching speed (

Operating properties of charge-trapping-type Flash memory devices with single or stacked structures on trapping layer are investigated in this letter. Improved operation and reliability characteristics can be achieved by adapting the stacked high-k films as charge-trapping layer due to the modification in the trap density and the energy level of traps, the mechanism of electron/hole transmission, and the suitable band offset. Moreover, with a small bandgap of second film in the stacked trapping layer, operating characteristics of devices are further enhanced.

A novel method of fabricating HfOx-based resistive memory device with excellent nonvolatile characteristics is proposed. By using a thin AlCu layer as the reactive buffer layer into the anodic side of a capacitor-like memory cell, excellent memory performances, which include reliable programming/erasing endurance (> 105 cycles), robust data retention at high temperature, and fast operation speed (< 50 ns), have been demonstrated. The resistive memory based on AlCu/HfOx stacked layer in this letter shows promising application in the next generation of nonvolatile memory.

TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≤50 μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.

A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

TSV (through silicon via) metallization is one key process in 3DIC integration. Due to high aspect ratio and filling volume, TSV copper plating is the most time-consuming module in the whole process flow. To increase the throughput of electroplating, tool configurations and plating chemistry should be optimized. In this work, an electroplating chamber with a novel paddle design is used in this experiment to study the effects of paddle agitation on plating performance. The influence of this paddle design on different TSV pattern density and geometric scheme are also investigated.