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We investigate the determining mechanisms of the inversion-layer capacitance Cinv in the high-k/metal gate stacks, focusing on the two perturbative effects related with the dielectric properties. Those effects are the penetration of inversion-layer carriers into the dielectrics with a finite potential barrier and the image potential acting on the carriers adjacent to the dielectrics with permittivity different from that of the silicon substrate. The experimental and the theoretical analyses of the Cinv dependency on the crystal orientation of silicon substrates enable us to separate the two effects and to prove that the observed Cinv modulation in the high- k/metal gate stacks is attributable not to the image potential effect, but to the penetration effect. Moreover, we investigate the reduction of the total gate capacitance due to the Cinv in the advanced gate stacks scaled down to 0.66-nm equivalent oxide thickness. The influence of the elementary composition, the physical thickness, and the interface layer on a scaling loss due to the Cinv is experimentally evaluated.

We report fully-depleted UTBB devices with a gate length (LG) of 25nm and BOX thickness (TBOX) at 25nm, fabricated with a 22nm technology ground rule, featuring conventional gate first high-K/metal and raised source/drain (RSD) process. Competitive drive currents are achieved. Effective Vt modulation is observed with back bias (Vbb) and different ground plane (GP) polarity. Excellent local Vt variation is demonstrated. A functional UTBB 0.108μm2 6-T SRAM is reported with Vdd down to 0.4V. We also present simulation studies that suggest UTBB device has superior scalability compared with thick BOX ETSOI device, thanks to better short channel effect (SCE) control.

The inversion-layer capacitance Cinv of electrons in high-k/metal gate stacks (HKMGs) is studied theoretically and experimentally from the viewpoint of the penetration of electrons into the dielectrics. The numerical calculation of Cinv in the dielectric/substrate bilayer structure has clarified the influence of penetration on Cinv . Cinv in an HKMG is evaluated experimentally and is compared with the computational predictions in terms of the dependence on the dielectric boundary and the silicon crystal orientation. The consistency of the experiment and the calculation is the first evidence for the considerable modulation of Cinv due to penetration in the actual HKMG. Moreover, the dependence of Cinv on substrate biasing is investigated. The detailed analysis of Cinv in the system where the confinement of the inversion layer is intentionally changed has led to a further understanding of Cinv determined by penetration.

In this paper we will review some of our previous work on ALD deposited high-K dielectric stacks as well as present some of our more recent advances. We have shown that ALD can be used successfully to deposit high quality high-K gate dielectrics of Hf and Zr oxide. In addition, because of the inherent conformality of ALD processes, these dielectrics can be easily migrated to advanced device structures such as FINFETs. We have also been successful in developing ALD processes to deposit rare earth oxides (REOs), such as Y2O3 and La2O3. These processes are useful in creating layered dielectric structures where the REO functions as a threshold voltage adjustment layer. We use physical and electrical characterization of the films as deposited by ALD, including spectroscopic ellipsometry, corona oxide semiconductor charge measurement, TXRF, AES, angle resolved XPS, HRTEM, AFM, MEIS, and RBS, to provide information on the film growth mechanism and the primary parameters that influence the ALD growth of high-K oxides. We further correlate these findings with basic electrical results obtained from MOSFET and MOSCAP devices fabricated using our ALD processes to understand how process changes affect both the as-deposited films as well as the resulting devices.

A threshold voltage lowering of up to 400 mV in HfSiON/polycrystalline silicon (poly-Si) gate stack p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) by fluorine incorporation into the channel is observed. Physical analysis verifies that implanted fluorine exists only in the channel region. The characteristics of the short-channel devices are investigated in detail, and an acceptor generation model by fluorine implantation is proposed. The model successfully explains the characteristics of fluorine-incorporated short-channel pMOSFETs.

The understanding of the mechanism of Vfb shift and the improvement of the [N]-Vfb shift relationship are essential for realizing SiON film with superior device performance. By forming the smooth SiN film with high-density N-Si3 structure and suppressing the deterioration of Si-N network due to oxidation, SiON films dramatically improved in terms of the [N]-Vfb shift relationship, with ultra-thin EOT (0.71 nm), ultra-low leakage current (134 A/cm2) and high Gm max (115%), are realized. The middle temperature and low-pressure nitridation and the optimization of oxidation conditions are the keys to forming defect-free perfect Si3N4 and SiON films and to achieving these performances.

High-k/metal gate stack is highly expected in 32 nm generation CMOSFETs. However, adjustment of threshold voltage, Vth, is still the major challenge for high-k/metal gate CMOSFETs at this point. This paper reviews the current situation and suggested solutions of Hf-related gate dielectrics/metal gate stacks mainly focused on work function control.

We have investigated the reaction mechanism of the nitridation process based on first principles calculations and experimental results. We found that oxidation-resistant Si3N4 film can be formed by uniformly arranging 3-fold coordinated N atoms into Si sub-surface layer, and we successfully incorporated O atoms into the SiN/Si interface with minimum disruption of SiN structures. We have realized a high-quality ultra-thin gate SiON film with an equivalent oxide thickness of 0.7 nm and a leakage current of 95 A/cm2, 1/10 or less than that of traditional SiON films. Mobility is not reduced to less than 89% of an ideal SiO2 film.

Insulators with high dielectric constants (so-called high-k) have been intensively investigated for the replacement of SiO2 gate dielectric of MOS transistors for high-speed ULSIs in near future. The characterization results of the Hf-silicate gate dielectric, especially in terms of its structural transformation during high temperature annealing, are presented. Phase separation and micro-crystallization in Hf-silicates were evaluated using XPS, TEM, and XRD. Impurity diffusion through the dielectric was also examined using the backside SIMS of the p+-poly-Si/Hf-silicate/Si-substrate system. It has also been revealed that such thermal stability problems for Hf-silicates can be solved with nitrogen incorporation in the film using the physical analyses outlined above. [DOI: 10.1380/ejssnt.2003.116]

The surface quantization effect below the gate insulator of MOSFETs is practically introduced into the device simulation by adding the quantum correction potential to the drift term of the current density equation. The quantum correction potential is calculated as a simple function of the distance from the surface by substituting Fang's trial function as the carrier density distribution into Ancona's density-gradient method. The effective mass perpendicular to the surface is adjusted to reproduce Schrodinger–Poisson calculations. Simulation results of the gate voltage dependence of the gate capacitance are compared with experimental results. It is demonstrated that the present approach could be a robust tool by showing simulations combined with the energy transport effect.

In this paper, the results of the direct measurement of inversion-layer mobility for metal-oxide-semiconductor field-effect-transistors (MOSFETs) with ultrathin gate oxides, based on the split C–V method are reported. It was demonstrated that inversion-layer electron mobility can be accurately measured for MOSFETs with gate oxide thickness of down to 1.5 nm by the split C–V method with modified measurement of drain conductance under optimum device size and measurement conditions. It was found that, when gate oxide thickness is less than 3 nm, the mobility deceases in the low surface carrier concentration (effective field) region with a decrease in gate oxide thickness and that this mobility lowering becomes smaller in the higher surface carrier concentration (effective field) region. It was also found that mobility limited by some additional scattering observed in thin gate oxides has almost no surface carrier concentration dependence.

This paper presents the experimental results of the carrier conduction mechanism in thin gate oxides after soft and hard breakdowns, obtained from the carrier separation technique. This technique allows the identification of the dominant carrier type on the gate leakage current, which is shown to be an important factor for clarifying the physical picture of breakdown spots. The carrier conduction after hard breakdown is shown to be dominated by the majority carrier in the poly Si gate, meaning that the poly Si gate is directly contacting a Si substrate after hard breakdown. It is found, on the other hand, that hole current becomes dominant on the leakage path after soft breakdown. This difference in dominant carrier type between soft and hard breakdown suggests that the ultrathin oxide region still remains in the leakage path after soft breakdown. The dominance of hole current is attributable to larger tunneling probability of holes than that of electrons through the extremely-thin oxide region remaining after soft breakdown.

The influence of inversion-layer capacitance (C/sub inv/) on supply voltage (V/sub dd/) of n- and p-MOSFET's is quantitatively examined. The physical origin of the effect of C/sub inv/ on V/sub dd/ consists in the band bending of a Si substrate in the inversion condition due to C/sub inv/, which is not scaled with a reduction in gate oxide thickness. The amount and the impact of the band bending is accurately evaluated on a basis of one dimensional (1-D) self-consistent calculations including two-dimensional (2-D) subband structure of inversion-layer electrons and holes. It is demonstrated that additional band bending of a Si substrate due to C/sub inv/ becomes a dominant factor to limit the lowering of V/sub dd/ for CMOS with ultrathin gate oxides. The operation at V/sub dd/ lower than 0.6 V is quite difficult even with effective T/sub ox/ less than 1 nm.

Inversion-layer capacitance (C/sub inv/) in p-channel Si MOSFET's is studied experimentally and theoretically with emphasis on the surface carrier concentration (N/sub s/) dependence, which is important in the quantitative description and the physical understanding. The amount of C/sub inv/ and its influence on the gate capacitance are compared between electron and hole inversion layers. It is experimentally verified that, under same physical thickness of gate oxides, the electrical gate oxide thickness, determined from the gate capacitance, is larger for inversion-layer holes than that for inversion-layer electrons, because of smaller values of C/sub inv/ for inversion-layer holes. Self-consistent Poisson-Schrodinger calculation of C/sub inv/ is performed on basis of the approximation of a constant effective mass and is compared with the experimental C/sub inv/. It is found that the calculation using the effective masses at the valence band edge can accurately represent the experimental results over a whole range of N/sub s/.

Tamibarotene-loaded biodegradable matrices with antithrombogenic and drug-releasing properties were prepared in a crosslinking reaction between amino groups of alkali-treated collagen (AlCol) and active ester groups of trisuccinimidyl citrate. The resulting matrices were characterized by their residual amino group concentrations, swelling ratios and thermal, antithrombogenic and drug-releasing properties. It was clarified that the addition of tamibarotene does not inhibit matrix formation. After immersion in water, the swelling ratio of a matrix became lower than that prior to immersion. Thermal analysis indicated that AlCol interacted with tamibarotene. The addition of tamibarotene to the matrix did not influence the antithrombogenic property of the resulting matrix. A matrix with a high crosslinking density had a prolonged tamibarotene elution time. These results demonstrate that tamibarotene-loaded matrices have great potential as a coating material for drug-eluting stents.

A novel citric acid-crosslinked gelatin matrix with endothelialization activity and anti-adhesive properties for platelets is prepared. The matrix is characterized using an endothelial cell culture and an antithrombogenic activity test. The number of endothelial cells cultured on the surface of the trisuccinimidyl citrate (TSC)-crosslinked gelatin increases as the concentration of TSC increases to 20 mM, and then decreases with further increases in TSC concentration. Compared with glutaraldehyde-crosslinked gelatin, platelet number and fibrin network formation on the TSC-crosslinked gelatin are minimal at high TSC concentration. The biocompatibility of the matrix is evaluated by bioluminescence imaging. This indicates that the inflammation reaction of the TSC-crosslinked gelatin is lower than that of glutaraldehyde-crosslinked gelatin. Physicochemical analysis of TSC-crosslinked gelatin with different TSC concentrations shows that the high concentration of the cell adhesion sequence, arginine-glycine-aspartic acid, contributes to the promotion of endothelial cell adhesion and subsequent endothelial cell growth. Analysis of the carboxyl groups in the TSC-crosslinked gelatin showed that the antithrombogenic activity is due to the increased negative charge derived from the hydrolyzed active ester groups of TSC. These findings show that TSC-crosslinked gelatin has the potential for use in biomedical devices in contact with blood, such as stents, artificial blood vessels, and artificial heart valves.

We show a new Ge channel ion implantation scheme for realization of low-V TH pFET, which enables ∼500mV V TH lowering with no T inv , GIDL and NBTI degradations. We also reveal the physical origin of the large V TH modulation. Based on experimental findings, we propose simplified photo-resist masked dual low-V TH CMOS flow and demonstrate low-V TH pFET/nFET operations.

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

We present UTBB devices with a gate length (L G ) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V bb ) enables V t modulation of more than 125mV with a V bb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V t and power management applications. We explore the impact of GP, BOX thickness and V bb on local V t variability for the first time. Excellent A Vt of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I g ) and lower external resistance (R ext ), thanks to a thicker inversion gate dielectric (T inv ) and body (T si ) thickness.

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (R para ) degraded by 3-D structure with thin Si-body. The issue of V t -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

We have demonstrated the complete copper filling of contact structures at 32 nm- and 22 nm-node dimensions with the conventional PVD only Ta(N)/Cu barrier/seed process. Copper seed process was optimized to obtain the sufficient coverage of copper along the contact hole with the sufficiently wide gap opening at the top by the use of the directional sputtering and the re-sputtering techniques. In addition, this process was implemented on fully integrated 32 nm-node device wafers and the optimized process produced sufficient performance to meet 32 nm-node requirements. The investigation also included two cases with intentional departure from the optimal conditions, one with a low thickness barrier and the other without copper re-sputtering. In both cases negative influence on front-end-of-the-line (FEOL) parameters was observed.

A new expression for the band-to-band tunneling in the presence of a nonuniform electric field is derived, with emphasis on the importance of the exact evaluation of integrals over wave vectors of a tunneling electron. Nonuniformity of the electric field is taken into account in calculating the interband matrix element, although it is neglected in the electronic wave functions. Nonuniformity of the electric field tends to decrease the tunneling rate. The new expression shows a different electric field dependence from E.O. Kane's (1959, 1961) tunneling rate especially in high electric fields. The appropriate evaluation of wave-vector integrations and the consideration of the spatial dependence of the electric field are indispensable to obtaining a correct electric-field dependence of the tunneling rate. >

Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell, at Vd = 0.6 V, a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. sigmaVt of transistors in 0.187 m2 cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, which would have higher sigmaVt mainly caused by heavy doping into the channel region.

Temperature (T) dependence of threshold voltage (Vt) for high-k metal gate stack (HK/MG) CMOS is investigated thoroughly. It is found, for the first time, that T dependence of Vt (dVt/dT) for HK/MG CMOS shows asymmetrical behavior between N and PFETs unlike conventional Poly-Si/SiON CMOS. Moreover, this dVt/dT asymmetry is observed even if capping techniques for Vt tuning are applied to high-k dielectrics. The position of effective Fermi level in HK/MG (EFM,eff) is determined quantitatively in a wide range of T by experimental and theoretical analysis for the first time, which reveals that the off-center arrangement of EFM,eff in Si band gap is the cause of dVt/dT asymmetry not only in the long channel region but also in the short channel region. In addition, based on these analyses, dVt/dT for aggressively thinned FinFETs with HK/MG is predicted.

Twisted direct silicon bonded (DSB) substrate demonstrates a higher hole mobility advantage over (110) bulk substrate for PFET. The mobility shows a (110) layer thickness dependence with the thinner DSB layer having a higher hole mobility. 25% on-current improvement is obtained for thin DSB PFETs at long channel (Lg= 2 mum), 10% higher at short channel (Lg = 36 nm) compared to (110) bulk PFETs. Moreover, we found that the thinner DSB shows better Vt roll-off characteristics. On the other hand, NFETs on DSB are as good as (100) bulk NFETs. Thin DSB substrate demonstrates 11% faster ring oscillator speed over thick DSB substrate and 30% faster over (100) bulk due to higher mobility and lower capacitance.

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1times10-8 Omega-cm2 for both n+ and p+ Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.

End-of-range (EOR) defects generated during the crystal orientation conversion process in DSB technology can give rise to various types of junction leakage depending on their locations relative to device structures. A wide range of EOR defect depths are investigated. Shallow-implant-induced EOR defects (~100 nm) are found to minimize junction leakages due to EOR defects being outside of junction depletion regions. These implant conditions produce no adverse impact on source/drain channel leakage, suggesting that the crystal conversion process is optimized by shallow implants.

A new synthetic polymer of aromatic polyether (APE), having a narrow distribution of molecular weight, formed a specific self-assembly of Langmuir film (L film) on a water surface, which was subjected to surface pressure relaxation when the L film was compressed over 16.5 mN m(-1) at 15 degrees C. This self-assembly was capable of transferring on silicon-wafers as LB films. We found that, because the XRD patterns for fabricated LB films depended on the crystal face of the silicon-wafer used and moreover increased in diffraction intensity with the increasing number of built-up layers in the LB film, the present LB films showed a kind of epitaxy-like phenomenon. We propose the molecular mechanism explaining that the formation of an ionic supuramolecular structure of APE occurs only on a silicon wafer surface.

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10-8 Omega-cm2 for both n+ and p+ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.

When DSB bonding interface falls into highly doped S/D direct silicon bonded (DSB) technology is shown to be scalable regions, there are concerns of high S/D leakage (due to the possible for 32 nm node and beyond for two integration schemes: solid phase defects in the DSB interface) and high S/D resistance due to epitaxy (SPE)-before-shallow trench isolation (STI) and STI-before-SPE. For SPE-before-STI, 32 nm node ground rules can be met by thinning DSB thickness to ~70 nm, which ensures complete removal of boundary defects by STI. For STI-before-SPE, a scaling-independent solution is provided by the use of 45deg rotated (100) base wafers which allow trench-defect-free SPE at the STI edges.

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12A) for BE nFET devices to-date, consistent with simulations showing the need for ≪14A T inv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin Tinv (≪13A) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

The electron mobility degradation for HfSiON MISFETs was investigated. We found that the degradation had two origins; one is Coulomb scattering caused by fixed charges in HfSiON films and the other is phonon scattering by interfacial thin oxynitrided (SiON) layer; and HfSiO-related remote phonon scattering is not dominant. The mobility degradation caused by the Coulomb scattering and SiON phonon scattering is separated into two components and we develop an empirical mobility model for HfSiON devices that enables accurate simulation of electrical characteristics of the HfSiON devices

The understanding of the mechanism of Delta Vfb and the improvement of [N]-DeltaVfb relationship are essential for realizing SiON film with superior device performance. By forming the smooth SiN film with high-density NequivSi3 structure and suppressing the deterioration of Si-N network due to oxidation, SiON films with dramatic improvement on [N]-DeltaVfb relationship with ultra-thin EOT (0.71 nm), ultra-low leakage current (134 A/cm2) and high Gm max (115%) is realized. The middle temperature and low pressure nitridation and the optimization of oxidation conditions are the keys to form defect-less perfect Si3N4 and SiON film and to achieve these performances

Inversion-layer mobility in highly doped channel Si MOSFETs was investigated. It was found, for the first time, substrate Coulomb scattering (musub) has anomalous surface carrier density (N S) dependence when acceptor concentration (NA) becomes larger than 2times1018 cm-3. The mu sub behavior can be explained by the suppression of the screening effect. In addition, interface Coulomb scattering (muit ) has stronger NS dependence than ever reported. The muit behavior can be explained in terms of the relative distance between the surface carriers and interface states. Influence of high channel doping on MOS interface barrier height was also studied

Dominant scattering mechanisms for both electrons and holes in HfSiON MISFET were examined systematically by using the newly developed pulse measurement technique. Mobility determining factors for electrons and holes in various effective field (Eeff) regions were identified. In addition, the influence of two elements of Hf and N on the mobility in the operational Eeff region was investigated and guidelines for improving performance of HfSiON-CMOS devices were presented

Vth control technology of HfSiON gate dielectrics by channel engineering using counter ion implantation method and fluorine or nitrogen ion implantation method are described. Current Ni-FUSI gate technology is also mentioned. Moreover, the authors explain breakdown mechanism of poly-Si/HfSiON/SiO2 gate stacks

A prediction model for the breakdown voltage of ultra-thin gate insulator in electrostatic discharge (ESD) is proposed. The time-dependent-dielectric-breakdown characteristics under DC stress successfully predicts ESD oriented dielectric breakdown on the basis of the modified anode hole injection model. The proposed model redistributes experimental breakdown voltages and number of pulses to breakdown in extensive gate voltages and gate insulator thicknesses. In conclusion, the present model is quite effective for the prediction of ESD reliability in highly scaled ULSI devices.

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, the authors discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in Svg with technology scaling according to the ITRS roadmap based on Mikoshiba's model

Based on experimental results, the lifetime projection of breakdown and its mechanisms in HfSiON dielectrics were discussed. In HfSiON dielectrics, the total hole fluence to breakdown (Qp) was not found to be a dominant factor. We propose that the thermochemical breakdown along with the acceleration by injected carriers is the primary degradation mechanism in HfSiON dielectrics, especially at high temperature.

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.

In this paper, the effect of the MIGS and the poly-Si process on the Vfb shift was carefully examined and clarified. We conclude that these factors are not correlated with the shift. We found that lowering the Htf (Hf+Si) (Hf-ratio) in HfSiON below 10% leads to the significant suppression of this shift in both NMOS and PMOS. We also demonstrated that the insertion of ultra-thin cap layers into the poly-Si/HfSiON results in Vfb improvement with 0.1 nm EOT expense. We proposed that the sophisticated tailoring of Hf in the dielectric could be a practical solution for the Vfb improvement.