Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gatestack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense

In this paper, the effect of the MIGS and the poly-Si process on the Vfb shift was carefully examined and clarified. We conclude that these factors are not correlated with the shift. We found that lowering the Htf (Hf+Si) (Hf-ratio) in HfSiON below 10% leads to the significant suppression of this shift in both NMOS and PMOS. We also demonstrated that the insertion of ultra-thin cap layers into the poly-Si/HfSiON results in Vfb improvement with 0.1 nm EOT expense. We proposed that the sophisticated tailoring of Hf in the dielectric could be a practical solution for the Vfb improvement.