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Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T Experiments were carried out in an Applied Materials epitaxy reactor featuring (i) liquid precursor delivery, together with H2, N2 or He carrier gas capability, enabling the use of Cl2; (ii) “High Precision Temperature Control (HPTC)”, allowing excellent LT control and enabling flexible rotation speeds; (iii) “precision flow distribution PFD-III”, enhancing uniformity performances. Selective Epitaxial Growth (SEG) is usually obtained with “co-flow” processes at rather high temperatures (>600°C). Chlorinated precursors (SiH2Cl2 (+ GeH4) + HCl, typically) are then sent simultaneously into the growth chamber. At LT ( This strategy allowed us to obtain high quality films, as shown in Fig.1. The Omega-2Theta scans around the (004) X-Ray Diffraction order for tensile SiP (t-SiP) layers grown at T < 500°C with different Phosphorus concentrations were indeed typical of monocrystalline layers, with well-defined and intense peaks together with numerous thickness fringes. The substitutional P contents in those ~ 60 nm thick t-SiP layers were in the 1.02% - 5.42% range. The good layer uniformity in terms of thickness and P content, over a 300mm wafer radius, is shown in figure Fig.2. These layers grown at T Fig.3, with a 0.21 nm Root Mean Square (RMS) roughness for a 60nm thick Si:P layer, i.e. a value close to the typical RMS roughness for t-SiP layers grown at high temperature with a chlorinated chemistry. The electrical resistivity in various t-SiP layers is plotted in Fig.4 as function of the substitutional phosphorus concentration and for various growth temperatures in the 450°C – 525°C range. Reducing the temperature by 75°C halved the electrical resistivity. We were able to achieve a resistivity as low as 0.21 mOhm.cm for a t-SiP layer with 5.8% of P grown at 450°C. We then evaluated, at first on tests structures without gates, our process selectivity. A top view Scanning Electron Microscopy image of a t-SiP layer grown non-selectively, with numerous amorphous SiP nuclei on SiO2, is shown in Fig 5.a. After some careful optimization, we succeeded in having fully selective processes versus SiO2, as shown in Fig 5.b. We then tested such optimized processes on low density FD-SOI devices with 28 nm design rules. A top-view SEM image of transistors after such a growth is shown in Fig.6. The growth selectivity was excellent, with nitride spacers and hard masks as well as isolations free of a-SiP nuclei for 31 nm of t-SiP with 4.5% of P deposited in the Sources/Drains. The surface was smooth, with a RMS roughness as low as 0.30nm on active areas, as shown in Fig.7. Thanks to High Resolution Reciprocal Space Maps (HR-RSM), we measured a Phosphorus concentration of 4.5% for that SiP layer grown on SOI. The very high quality of that epitaxy layer, with well-defined thickness fringes, is obvious in Fig.8. Cross-sectional Transmission Electron Microscopy (TEM) images such as the one shown in Fig. 9 enabled us to confirm, at the nanoscale, the excellent quality of such layers in RSDs. To sum up, we were able to develop a tensile Si:P process which was shown to be selective, at a temperature lower than 500°C, against SiO2 and SiN. Such t-SiP layers were successfully integrated in the Sources/Drains regions of FD-SOI 28nm devices. The very low material resistivity and the high phosphorus content should yield, notably because of tensile strain, performant NMOS devices in the near future. [1] C. Fenouillet-Beranger et al., IEEE TED 68, 3142-3148 (2021) [2] V. Chan et al., IEEE 2005 Custom Integrated Circuits Conference 2005, pp. 667-674 Figure 1

Abstract— To support 3D Sequential integration with a cost-effective layer transfer, SmartCut™ process at low temperature (below 500 °C) is proposed. Excellent SOI & BOX layer thickness uniformities are demonstrated, while layer integrity, electron and hole mobility performances are already compliant with development grade requirements. Keywords—SmartCut, 3D Integration, Low Temperature, CMOS I. SmartCut Proposal for 3D Sequential Integration In support of the semiconductor evolution, 3D integration is considered, addressing several challenges: integration of multiple types of devices including specialized components, continuous footprint reduction as well as optimization of performance and cost [1]. However, a key challenge for 3D integration, shown on Figure 1 reported in reference [2], is the preparation of a top tier device using as handle surface a fully processed bottom tier device. Hence, the top tier device thermal budget needs to be reduced to avoid degradation of the bottom devices [3]. A mandatory 500 °C thermal budget limitation for 3D Sequential Top layer transfer and MOSFET fabrication is then considered [2, 4]. In order to take advantage of the SmartCut process to transfer at reduced cost (i.e. avoiding a conventional but costly SOI bonding & grinding process) a high quality, highly uniform crystalline layer, we propose the use of a new Low Temperature SmartCut process as an alternative for 3D integration. This paper reports on our findings from such transfer demonstrations on bare handle materials, including for the first time SOI-like layer electrical characterization results. II. Low Temperature SmartCut for 3D Integration For 3D integration, SmartCut process is adapted as schematically shown on Figure 2 in order to transfer at low temperature ultra-thin layers compatible with fully depleted requirements. This process option includes the use of engineered, epitaxial processed donor wafers. The epitaxial process on conventional bulk material allows creation of a first Silicon-Germanium layer, to be used as an etch stop layer after SmartCut splitting. Then a subsequent Si layer, defined accordingly to the SOI film thickness target, is epitaxied. Implant, surface preparation, bonding, splitting process steps, all being compliant with maximum 500 °C low temperature requirement, benefit from conventional FD-SOI experience. Finishing process includes selective etching to recover SOI layer [5]. Then a dedicated curing process step is considered in order to optimize SOI layer electrical properties. Silicon Phase Epitaxial Regrowth (SPER) as described in reference [6] is proposed. Figure 3 highlights such low temperature layer transfer process on a patterned handle wafer. Picture is obtained after SmartCut splitting process step. A visual defect free layer is obtained. III. Low Temperature SOI Performance on Bare Handle wafer The SOI layer thickness variability, over the full spatial wavelength spectrum from device to wafer scale, is driven by the donor epitaxy performance. Figure 4 shows Atomic Force Microscopy (AFM) roughness performance, through 30x30 µm² scan. RMS of 1.0 and 0.9 Å are measured on high and low temperature process options respectively. Best in class performance is then obtained thanks to Low Temperature SmartCut. Figure 5 shows (a) BOX and (b) SOI layers ellipsometry thickness mapping, on a 12 nm SOI / 20 nm BOX sample. BOX layer variability is primarily driven by thermal oxide growth, thus demonstrating a within wafer uniformity << 10 A. SOI layer thickness variability is mainly driven by epitaxy performance on the engineered donor wafer. Figure 6 shows typical KLA Tencor SP3 @ 65 nm threshold defect mapping, as measured on 12 / 20 nm low temperature R&D sample. Micro-defect density on this early development product already demonstrates less than 0.1 defect / cm² performance. Then Figure 7 compares PsiMOS measured electron and hole mobility in the SOI layer using High and Low Temperature SmartCut processes. A as low as 10% mobility performance difference between both processes vintage is already demonstrated. IV. Conclusion To support 3D sequential integration, layer transfer at low temperature (< 500 °C) is demonstrated thanks to an adapted SmartCut process. Next research step will confirm this capability with low temperature layer transfer on patterned substrate for 3DS device assessment. V. References [1] J. Macri, Proc. IEEE S3S Conference, 2018 [2] L. Brunet et al., Technical Digest – IEDM Conference, 2018, pp 7.2.1 – 7.2.4 [3] A. Vandooren et al., Proc. IEEE S3S Conference, 2018 [4] C. Fenouillet-Beranger et al., Proc. IEDM Conf., 2014. [5] J. Widiez et al. ECS Trans., 2014, vol. 64(5), pp. 35-48 [6] G. Gaudin et al., ECS J. Solid. State. Sci Tech., 2(12), 2013, pp 534 - 538 Figure 1

Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/ ${f}$ ) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/ ${f}$ noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GHz for a gate length of 45 nm and ${V}_{\text {DD}} = -1$ V. Moreover, we demonstrate that the low- ${k}$ SiCO oxide spacer and low polysilicon gate resistance obtained with the low temperature process contribute to ${f}_{\text {max}}$ results that are better than high temperature process (above 1000°). Finally, we illustrate the crosstalk effects and the influence of the low-tier transistor gate voltage ${V}_{\text {G}}$ on the top-tier threshold voltage ${V}_{T}$ . We also show that a polysilicon ground shield integrated under the top-tier transistor substantially attenuates the intertier RF field coupling effects.

The impact of interface charges under the gate spacer on FDSOI devices integrated in low temperature process are explored. A great number of traps (~1013/cm2) are identified on the interface between the spacer oxide and the silicon film using Terman's method for interface states characterization. Thanks to electrical characterization and TCAD simulations, it is shown that the trapped charges induce the formation of a depleted region in the vicinities of the spacer. Moreover, a strong degradation of performances on underlap channels is observed. The spacer charges influence on reliability measurements is finally explored.

We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m matching, $A_{v0}=62dB$ gain (L=200nm), $f_{T}=126GHz$ cut-off frequency and $f_{MAX}=182GHz$ maximum operating frequency (L=35nm). Junction Less transistor performances even exceed those of inversion-mode ones in terms of back-bias capability, low-frequency noise, hotcarrier degradation and fMAX. This is explained by junction less physics: channel length modulation, bulk conduction and high channel-depth sensitivity to back bias.

International audience; This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.

International audience; For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for the dynamic coupling effects and their impact is investigated for a 3D sequential 2-bitcell SRAM cell circuit configuration. Furthermore, we show a greater than 20dB suppression up to 100GHz of the inter-tier RF crosstalk, achieved by the addition of a strategically designed polysilicon Ground Plane between active device layers enabling the possibility of heterogeneous 3DSI integration without metallic Ground Plane. We propose a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltage (VDD) and back bias (Vwell) are extracted. These data evidence that the 14nm SRAM is read-limited, which could be improved by a smart back-bias management [1]. In this work we demonstrate a 50mV Static Noise Margin (SNM) variability improvement (at VDD=0.8V) by back-biasing, without additional Bias Temperature Instability (BTI) stress. Such an assist technique can be eventually leveraged at fine-grain by 3D monolithic integration, owing to local back-planes.

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) $0.078\mu \mathrm{m}^{2}$ SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at $V_{DD}=0.8\mathrm{V}$ and a reduction of minimum operating voltage $V_{min}$ by 60mV at $6\sigma$ w.r.t. planar SRAMs.

International audience; This work presents for the first time an analytical study of the electrostatic coupling between bottom and top layer of 3D sequential integration devices, regarding its impact on both static and noise behavior. The effect is demonstrated experimentally through statistical measurements, and TCAD simulations are used to further examine its properties and propose ways for the limitation of inter-tier coupling. It is demonstrated that regarding digital applications, the coupling-induced fluctuations are well within the mismatch variation level.

This paper highlights the last technological breakthroughs achieved in the development of low temperature process modules at 500°C for 3D sequential integration. The two remaining process steps (low temperature gate stack and selective silicon raised source drain epitaxy) that were considered as potential showstoppers for this technology have shown decisive progress very recently.

International audience; Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin.

session 3: Characterization technqiues and reliability assessment techniques; International audience

session T8: Transistor; International audience; For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) 0.078µm 2 SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at VDD=0.8V and a reduction of minimum operating voltage Vmin by 60mV at 6w.r.t. planar SRAMs.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage Vmin by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs.

session T7: Process and Material Technology; International audience; We investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS.

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $\mathrm{T}_{\text{TOP}}=500^{\circ}\mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

In this paper, we review the main opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. Simulation results show that 3D monolithic integration can provide up to 30% power reduction at iso-performance and 30% manufacturing cost saving for digital circuits, compared to planar technology, making it an attractive alternative to the straightforward technology scaling. We benchmark the transistor-level and cell-level 3D-monolithic integrations, where the inter-tier vias (3D-contacts) are used intra-cell or inter-cell, respectively. On the one hand, transistor-level 3D-integration can be seen as a full-custom approach, both in terms of technology and circuit design. It promises more performance but at the expense of strong Design/Technology Co-Optimizations. On the other hand, the cell-level 3D-integration ensures a 50% area reduction and a re-use of the technology/design platform. The main technology challenge relative to this integration is the thermal budget constraint of the top-level process integration and the intermediate Back-End-Of-Line (iBEOL) stability. Finally, the total isolation of the top-level transistors integrated in 3D-monolithic raises new opportunities and offers new functionalities like for example an efficient dynamic back-biasing capability.

session 7: Characterization, Reliability, and Yield: Reliability of Advanced Devices (7.6); International audience; We present for the first time an experimental study of thermal effects in 3D sequential integration, including Self-Heating Effect (SHE) and thermal coupling between the two levels of ultra-thin body FDSOI transistors. We extracted a large set of experimental data using different thermometry techniques, and different heater-sensor configurations allowed by this specific stacked integration. We described SHE in top and bottom transistor levels, as well as the influence of a transistor in ON state on a transistor stacked above or below. At the same time, we provide for the first time an experimental validation that the temperature increase given by gate resistance thermometry technique is equal to the temperature in the channel given by the subthreshold slope. Finally, this work can be also used to manage thermal effects for logic or analog applications, and help further optimization of 3D sequential integrated circuits through both technology and design solutions.

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (Ion) / OFF-state current (I off ) tradeoff than in single-gate (SG) mode. Moreover, a 3D-shared contact between a top and bottom electrode is experimentally demonstrated; paving the way for a local back gate, possibly connected with the top gate by a 3D-shared contact. Assuming such a construct, we have performed extensive layout and spice simulations of standard cells and SRAMs. We evidence that the back-gate overlap on the source and drain must be minimized to mitigate the parasitic capacitances. The best layout configurations of a loaded 1-finger inverter yields a 24% frequency gain at a given static power and V dd = 0.6V supply voltage, compared to SG, or to a static power divided by 5, compared to SG under Forward Body Bias (FBB). These performance boosts may be obtained without any area penalty and assuming a 20nm-thin BOX. Similarly, a 29% improvement of the read and write currents of 6T SRAMs is contemplated at V dd = 0.8V. Such new functionality provided by 3D-monolithic even enables making 4T SRAMs that are fully functional at V dd = 0.8V by improving their retention and, in turn, the maximum number of bitcells per column from 50 (SG) to 300 with a dynamic back-bias.

session: Modeling and Characterization; International audience; We present an experimental study of thermal effects in thin film FDSOI MOSFETs, with a focus on the impact of self-heating effect (SHE) on drain current. We have performed thermal resistance extraction using the gate thermometry method, and calculated the resulting cold drain current (Id0), i.e. without SHE. We demonstrate that SHE is more pronounced in shorter and narrower devices without essential differences between nMOS and pMOS transistors. Our experiments show that although the temperature increases significantly in the channel due to SHE, its effect on the ION performances could be limited at operating voltage.

session: Monolithic 3D 3; International audience; This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a -oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.

session B2L-G: Advanced CMOS Characterization and Reliability; International audience; — 3D sequential integration requires top FETs processing with a low thermal budget (500°C). The analysis of the origin of the performance difference between Low Temperature (LT) MOSFET and high temperature standard process must take into account a potential EOT modification for short gate lengths. In this work, the difficulty of precise EOT extraction for scaled devices is observed by CV measurements and an alternative methodology using IV measurements is proposed. This methodology has been applied to an extension first integration, and the extraction accuracy is high enough to conclude to an EOT regrowth for the low temperature nFETs only. Thus, the origin of performance degradation between LT and HT, previously attributed to larger access resistance, highlights also a detrimental role of gate stack instability. The origin of this variation is attributed to oxygen ingress, through the thin extension first liner which should be suppressed by minor process optimizations.

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

This study focuses on temperature deviation during operation of transistors inside a monolithic 3D standard cell built on two tiers. Early assessment of this topic is crucial to manage circuit design and requires both steady-state and transient thermal analysis at transistor level. A representative 3D standard cell in 14nm FDSOI technology is considered, using intermediate Back-End-Of-Line (iBEOL) and top tier BEOL. Steady-state and transient power dissipations in NMOS and PMOS are extracted from SPICE simulations with variables such as output load capacitance and operating temperature. 3D thermal simulations are then performed to assess the impact of design parameters such as routing densities, thicknesses of iBEOL and BEOL, their number of metal layers and packaging techniques. Steady-state and transient thermal simulations enable precise analysis to correlate temperature deviation of transistors with these parameters. Design guidelines are provided to limit the temperature deviation between top and bottom tier which can reach 7°Celsius during circuit operations in the worst case

This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.

Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained, leading to a 3D vias density over 108/mm2 achievable. In addition, we presented N-type devices fabricated below 630°C yielding quasi-equivalent performances as high temperature ones while fulfilling the PBTI and hot-carrier effects reliability requirements, comforting the viability of N over CMOS approach.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF2). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices with a unique connecting via density above tens of million/mm2. This results in increased devices density and gains in power and performance thanks to wire-length reduction without the extra cost associated to transistor scaling. In addition to power saving, this true 3D integration opens perspectives in terms of heterogeneous integration. We will review the opportunities brought by CoolCube™ and will present the most advanced technological demonstration of 3D CMOS over CMOS CoolCube™ integration.