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Laser Processing For 3D Junctionless Transistor Fabrication
- Source :
- 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
- Publication Year :
- 2020
- Publisher :
- arXiv, 2020.
-
Abstract
- To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.
- Subjects :
- 010302 applied physics
Materials science
Fabrication
business.industry
Annealing (metallurgy)
Doping
Transistor
0211 other engineering and technologies
FOS: Physical sciences
Physics - Applied Physics
02 engineering and technology
Applied Physics (physics.app-ph)
Nanosecond
01 natural sciences
Semiconductor laser theory
law.invention
law
021105 building & construction
0103 physical sciences
Optoelectronics
Wafer
business
Layer (electronics)
Subjects
Details
- ISBN :
- 978-1-72813-523-6
- ISBNs :
- 9781728135236
- Database :
- OpenAIRE
- Journal :
- 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
- Accession number :
- edsair.doi.dedup.....c9ce1f179d7606adeb1a27fcb299c07c
- Full Text :
- https://doi.org/10.48550/arxiv.2011.15061