Novel Fine-Grain Back Bias Assist Techniques for 14 nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic

session T8: Transistor; International audience; For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) 0.078µm 2 SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at VDD=0.8V and a reduction of minimum operating voltage Vmin by 60mV at 6w.r.t. planar SRAMs.