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Performance and Reliability of a Fully Integrated 3D Sequential Technology
- Source :
- 2018 VLSI-Technology Technical Digest, 2018 IEEE Symposium on VLSI Technology, 2018 IEEE Symposium on VLSI Technology, Jun 2018, Honolulu, United States. pp.75-76, ⟨10.1109/VLSIT.2018.8510625⟩
- Publication Year :
- 2018
- Publisher :
- HAL CCSD, 2018.
-
Abstract
- session T7: Process and Material Technology; International audience; We investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS.
- Subjects :
- 010302 applied physics
Computer science
Transistor
Process (computing)
02 engineering and technology
01 natural sciences
020202 computer hardware & architecture
PMOS logic
law.invention
Reliability engineering
Reliability (semiconductor)
law
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Inverter
[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
NMOS logic
Subjects
Details
- Language :
- English
- Database :
- OpenAIRE
- Journal :
- 2018 VLSI-Technology Technical Digest, 2018 IEEE Symposium on VLSI Technology, 2018 IEEE Symposium on VLSI Technology, Jun 2018, Honolulu, United States. pp.75-76, ⟨10.1109/VLSIT.2018.8510625⟩
- Accession number :
- edsair.doi.dedup.....33ffeae25bfb98a71b7c4cd8de991640
- Full Text :
- https://doi.org/10.1109/VLSIT.2018.8510625⟩