Search

An symmetric double-heater structure is proposed into the traditional stacked layer phase-change memory (PCM) for the first time. It contains no barrier layer. The superior multi-level storage (MLS) is verified in this structure by numerical simulation. Temperature at the interface of two phase-change materials is greatly reduced by reasonably choosing the heater radius, which is beneficial for less atomic interdiffusion at the interface, thus more stable MLS. Device performance can be optimized through material thickness trade-off. Hence, this structure is a candidate utility for the future MLS device

A new physical conductivity model of amorphous chalcogenide is proposed, based on carriers transport theory including hopping transport and trap-to-band transition. A numerical simulator based on this model is developed, and the simulation results agree well with the measurement. The ovonic switch voltage and current with different active area and temperature are studied based on the simulator, and the results show a good consistence with the measurement.

Parasitic capacitances of phase-change memory (PCM) bitlines which induce RC delay lead to reset failure. To analyze the critical parasitic capacitance of different feature sizes, the transient resistances of PCM cells with different geometries during programming is to be evaluated. In this work, an accurate numerical model including latent heat comparison (LHC) which is able to calculate transient resistance is developed, and a AlST-based PCM cell is simulated. Combining the transient resistance and the periphery parasitic circuit, the impact of the fall time during the end of reset pulse induced by parasitic capacitances is simulated. Results show that reset failure may happen during device scaling down. The method can be used to predict critical parasitic capacitance and critical size of PCM cells with different materials or structures.

The impact of junction formed by the electrode and bulk in phase change memory to conduction at the amorphous high resistance state is studied in this paper. Analytical model deduced from basic physical equation elucidates that the current changes from junction barrier limited to bulk barrier limited when the applied voltage increases. The currents deduced from the model are in highly consistent with the measurement data at different temperatures. It is also found that the junction barrier becomes non-negligible when the radius of bottom electrode is scaled down to 20 nm.

State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results show that the technique is effective in selecting the patterns which offer maximal power. It can be applied into the burn-in of logic circuits and SoCs in an energy saving manner.

This paper proposes two Design-for-Test (DfT) architectures for three-dimensional stacked ICs (3D-SICs) with a wireless test port. The two architectures use different test wrappers and TAMs, while the stack is partitioned into two subsets in both schemes. By testing the subsets simultaneously using the wired test port and the wireless test port, considerable test time can be saved. Optimization strategies of the two DfT architectures are discussed, and the total test time is estimated. Experimental results of both proposed optimal DfT architectures show that almost half of the total test time can be saved comparing with that of IEEE p1838 architecture.

Differential Power Analysis (DPA) reveals the secret key from the cryptographic device by side channel power leakage. Masking and Random Delay Insertion (RDI) are two countermeasures against DPA attack. But masking or RDI alone does not prevent DPA attack, they only enhance the difficulty of the attack. This paper proposes a novel countermeasure which associating masking with RDI. Furthermore, multi-masking instead of transformed masking is proposed in order to defend DPA attack based on hamming distance model. The combined countermeasure is implemented and verified on Data Encryption Standard (DES) algorithm. The results show that the combined countermeasure defends DPA attack with 105 power traces, and increases 40% ability against DPA with only 28% performance penalty.

This paper proposes a low-voltage power amplifier for the 3.0–5.0 GHz ultra-wideband applications. Based on the classical current-reused technique, it adopts a folded topology to achieve the low-voltage working with acceptable output linearity. Its two-stage amplifying configuration consists of only one NMOS and one PMOS transistors. Implemented in the 0.18 µm CMOS technology, it obtains a gain as high as 16 dB with only ±0.5 dB flatness over the full working band, and consumes only 23.2 mW with 0.75mm2 size under 1.2 V.

Physical defects in the cells of the NAND Flash memory fluctuate the current flowing through the memory string. Two oscillator ring based test schemes for NAND Flash memory are proposed. The oscillator ring scheme for single column has good diagnostic capability, and the double ring scheme are sensitive to both SA0/SA1 faults and some soft errors. Experimental results validated the effectiveness of these methods.

To speed up the deterioration of a circuit under test (CUT), an input pattern is needed to maximize its leakage power in the static burn-in process. This paper presents an efficient pattern generation method with ATPG approach. To reduce the effort of precise power calculation, a metric that is linearly related to the leakage power of CUT is proposed. This generation method reuses the test set for stuck-at faults, and it can search for the quasi-optimal target pattern in the collapsed pattern space by the equivalent fault model.

A new CMOS curvature compensated bandgap reference circuit which uses two different types of material to realize its resistors in an improved structure is presented. Implemented in a 0.18 μm technology, it achieves performance of a temperature coefficient of 1.8 ppm/°C over 0 ~ 100°C, a line regulation of 0.017%/V over the range 1.2 ~3 V and a power supply rejection ratio of 82 dB@1 Hz. It can offer a reference voltage of 1.1 V but occupy an area of only 0.049 mm2.

Differential Power Analysis (DPA) reveals the secret key from the cryptographic device by side channel power leakage. Masking and Random Delay Insertion (RDI) are two effective countermeasures against DPA attack. This paper propose a novel countermeasure which associating masking with RDI, further, Multi-Masking instead of Transformed Masking is proposed in order to defend DPA attack based on hamming distance model. The combined countermeasure is implemented on Data Encryption Standard (DES). The results show that combined countermeasure defends DPA attack with 105 power traces, and increases 40% ability against DPA.

A high gain 3-5GHz mixer merged with a very balanced wideband active balun is presented and demonstrated. It uses a Gilbert type folded structure with the active balun as the input trans-conductance stage and with a PMOS switch stage. The implemented circuit in the 0.18um CMOS technology exhibits less than 1dB amplitude imbalance in 2.06-5.2GHz, less than 1.5dB in 0.55-5.7GHz and less than 2 degree phase imbalance through 1.37GHz to 5.07GHz. The mixer exhibits a high IIP3 of -3dBm and a high isolation of LO-RF about -100dB in the wide bandwidth. It consumes only 6.2mW under a 1.8V power supply.

A new demodulation scheme for BPSK modulated first order derivative Gaussian pulses is proposed. The scheme first transfers the BPSK modulated data into the corresponding PWM modulated data, and filters out the narrower pulses to differentiate “0” and “1” state. The key idea of this method is based on detecting the modulated data pulse width. According to analysis of relevant paper, this method will fit the near field inductive coupling system for use like chip to chip wireless communication or centimeter range multimedia communications application. The simulation result shows that this demodulation method works well and supports hundreds of Megabits data rate (500 Mbps).

A high gain, wide band (2-10GHz) but low noise mixer is presented and demonstrated. It uses a Gilbert type folded structure with an active balun as the input trans-conductance stage and a PMOS switch stage. Because of the structure, each stage can be separately set its bias current to achieve high gain and low noise. The implemented circuit in the 0.18 um CMOS technology exhibits a high conversion gain (CG), 17.6 dB at 4 GHz and 8.1 dB at 10 GHz, a SSB noise figure (NF) of 15.6 dB, an IIP3 of -3.4 dBm to +2 dBm, and an isolation of RF-LO of -144 dB. The mixer power consumption is about 7.8 mW under a 1.8 V power supply.

A masking scheme of AES algorithm is analyzed, and the optimal masked S-box is implemented in this paper. By using the “tower field” representation, all nonlinear process of unmasked S-box is mapped to multiplication in GF(2), which is a single AND gate in circuits, and power consumption is hidden by using additive masked. In order to further reduce the hardware cost, a simplified masked AND gate is adopted and masks are reused safely. Both gate-level simulation and FPGA testing result have proved that our implementation provides good resistance against DPA attack.

Data retention is an important issue in the phase-change memories (PCMs) development, which is induced by the spontaneous thermal-driven crystallization for amorphous phase of chalcogenide material in PCMs. In this work, a data retention model for PCMs induced by spontaneous crystallization is presented. In this model, the spontaneous crystallization mechanism is modeled by nucleation and growth (N/G) theory, and Monte-Carlo approach is introduced to model the N/G process due to the stochastic nature of nucleation. According to this model, the resistance evolution with time is calculated. The model is calibrated by the experimental data, and results fit experimental data well. By defining the failure resistance, the statistical distributions of retention failure times are calculated, and the retention characteristics of PCMs are predicted.

Differential Power Analysis (DPA) is a powerful side channel attack method. Dual Rail Pre-charge Logic (DRP) is an effective circuit level DPA resistant countermeasure, however consumes more energy. Several adiabatic logic can resist differential power analysis attack while energy efficient. In this paper the comparison of DPA resistant ability for DRP logic and adiabatic logic will be presented and to make the comparison, a new criterion was introduced which could be used both for the DRP logic and adiabatic logic. Furthermore, the design issues for adiabatic logic will be discussed. Based on several standard cells and a full adder, the analysis results show that the ECRL logic has a good performance in DPA resistant ability (64%) as well as energy saving (83%).

Parasitic capacitance and resistance have much influence on the performance of the phase change memory (PCM). Based on SPICE circuit simulations, this paper investigates possible faults caused by the parasitic capacitance and resistance defects in stand-alone PCM cells. A realistic set of fault models are proposed and a test algorithm is proposed to test the faults.

SoC testing scheduling is an NP hard problem, and it is more complex for the hierarchical SoC architecture. By formulating the SoC testing scheduling problem as a 2-D bin-packing model, this paper solves the problem for the hierarchical SoC with the Ant Colony Optimization (ACO) algorithm to reduce testing application time. Experimental results on ITC'02 benchmark circuits show that the ACO algorithm is more effective than earlier proposed methods.

Previous results have suggested that spinosin, a C-glycoside flavonoid of Semen Ziziphi spinosae, potentiates pentobarbital-induced sleep via the serotonergic system. The present study investigated whether spinosin potentiates pentobarbital-induced sleep via serotonin-1A (5-hydroxytryptamine, 5-HT(1A)) receptors. The results demonstrated that spinosin significantly augmented pentobarbital (35 mg/kg, i.p.)-induced sleep in rats, reflected by reduced sleep latency and increased total sleep time, non-rapid eye movement (NREM) sleep time, and REM sleep time. With regard to NREM sleep duration, spinosin mainly increased slow-wave sleep (SWS). Additionally, spinosin (15mg/kg, i.g.) significantly antagonized 5-HT(1A) agonist 8-OH-DPAT (0.1mg/kg, i.p.)-induced reductions in total sleep time, NREM sleep, REM sleep, and SWS in pentobarbital-treated rats. These results suggest that spinosin may be an antagonist at postsynaptic 5-HT(1A) receptors because these effects of 8-OH-DPAT were considered to be mediated via postsynaptic 5-HT(1A) receptors. Moreover, co-administration of spinosin and the 5-HT(1A) antagonist 4-iodo-N-{2-[4-(methoxyphenyl)-1-piperazinyl]ethyl}-N-2-pyridinylbenzamide (p-MPPI), at doses that are ineffective when administered alone (spinosin 5mg/kg, p-MPPI 1mg/kg), had significant augmentative effects on pentobarbital-induced sleep, reflected by reduced sleep latency and increased total sleep time, NREM sleep, and REM sleep. In contrast to the attenuating effects of p-MPPI on REM sleep via presynaptic 5-HT(1A) autoreceptors, 15mg/kg spinosin significantly increased REM sleep. These results suggest that the effect of spinosin on REM sleep in pentobarbital-treated rats may be related to postsynaptic 5-HT(1A) receptors.

The bandwidth between automatic test equipment (ATE) and circuit under test is a bottleneck in the integrated circuit (IC) test. To reduce IC test time and cost, a novel variable shifting prefix-tail ID reverse (VSPTIDR) code for test stimulus data compression is designed in this paper. The coding rules and decoder are presented in detail. While the probability of Os in the test set is greater than 0.92, better compression ratio that acquire by VSPTIDR code contrasting with FDR code can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75% less than FDR decoder.

This paper presents a new method of human motion recognition based on MEMS inertial sensors data. A Micro Inertial Measurement Unit (μIMU) that is 56mm*23mm*15mm in size was built. This unit consists of three dimensional MEMS accelerometers, gyroscopes, a Bluetooth module and a MCU (Micro Controller Unit), which can record and transfer inertial data to a computer through serial port wirelessly. Five categories of human motion were done including walking, running, going upstairs, fall and standing. Fourier analysis was used to extract the feature from the human motion data. The concentrated information was finally used to categorize the human motions through HMM (Hidden Markov Model) process. Experimental results show that for the given 5 human motions, correct recognition rate range from 90%–100%. Also, a full combination of 6 parameters (G x , G y , G z , A x , A y , A z ) was listed and the recognition rate of each combination (total 63) was tested.

A 2-level FSK digital modems with CORDIC algorithm for family network is presented. The noncoherent detector is designed based on counting the zero crossings using new noise elimination technique. Synchronization control information is extracted from the magnitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1dB with frequency offset of 0.1MHz. The design is implemented with Xilinx VirtexII XC2V1000-4FG256 FPGA.

Based on the classical system design flow, a custom digital up converter (DUC) IP is designed and implemented for Homenet system. At the system level, DUC behavior model is constructed and DUC system architecture, spectra distribution scheme and circuit parameters are confirmed with system modeling tool MATLAB. At the circuit level, the main function modules such as interpolator and numerically controlled oscillators (NCO) and so on are designed and implemented. Considering the limited hardware resources and performance specification, a large number of optimizing technologies and algorithm are adopted. At last, Homenet system verification flat including our custom digital up converter system is realized with Xilinx Virtexll XC2V1000-4FG256 FPGA.

A reconfigurable CORDIC demodulator platform and design method for digital-IF receiver is presented. A 2-level FSK demodulator for family network is implemented and tested on that platform with Xilinx VirtexII XC2V1000-4FG256 FPGA. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination technique. Synchronization control information is extracted from the amplitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1dB with frequency offset of 0.1MHz