Search

We analyze the bit error rate (BER) performance of optical coherent communication systems employing multi-section monolithic tunable lasers with large excess phase noise. The BER of the coherent system utilizing a second-order decision-directed digital phase-locked loop (DD-PLL) for phase tracking was computed numerically. Experimental results have also been demonstrated with a 16-quadratic-amplitude modulation coherent system deploying a sampled-grating distributed Bragg reflector laser at 16 Gbaud that confirms the performance of the second-order DD-PLL in tracking the excess phase noise. [ABSTRACT FROM PUBLISHER]

As spatial division multiplexed transmission systems employing few mode fibers (FMFs) rely heavily on digital signal processing (DSP), the impact of computational complexity should be considered. A key DSP process block is the carrier phase estimation (CPE), which consists of a phase estimator and digital phase locked loop (DPLL) per output. In this letter, a low complexity phase estimator is proposed, and the common-mode laser frequency offset is exploited to reduce the number of DPLLs. The combination of a low complexity CPE and single DPLL is experimentally demonstrated for a 28 GBd six-channel transmission over a 41.7-km FMF, carrying up to 32 quadrature amplitude modulation. Thereby, the nonlinear tolerances for the proposed CPE scheme are shown to perform similarly as the more computationally complex conventional CPE scheme. [ABSTRACT FROM PUBLISHER]

We explore the spatiotemporal dynamics of a coupled map lattice (CML) system, which is realized with a one dimensional array of locally coupled digital phase-locked loops (DPLLs). DPLL is a nonlinear feedback-controlled system widely used as an important building block of electronic communication systems. We derive the phase-error equation of the spatially extended system of coupled DPLLs, which resembles a form of the equation of a CML system. We carry out stability analysis for the synchronized homogeneous solutions using the circulant matrix formalism. It is shown through extensive numerical simulations that with the variation of nonlinearity parameter and coupling strength the system shows transitions among several generic features of spatiotemporal dynamics, viz., synchronized fixed point solution, frozen random pattern, pattern selection, spatiotemporal intermittency, and fully developed spatiotemporal chaos. We quantify the spatiotemporal dynamics using quantitative measures like average quadratic deviation and spatial correlation function. We emphasize that instead of using an idealized model of CML, which is usually employed to observe the spatiotemporal behaviors, we consider a real world physical system and establish the existence of spatiotemporal chaos and other patterns in this system. We also discuss the importance of the present study in engineering application like removal of clock-skew in parallel processors. [ABSTRACT FROM AUTHOR]

Abstract: Nonlinear dynamics of a class of symmetric lock range digital phase-locked loops (SLR-DPLLs) has been investigated using nonlinear dynamical theoretical and computational tools. It has been observed that the system shows a period doubling route to chaos. For certain system parameters the loop exhibits intermittent behavior. The analytical bifurcation analysis shows that inspite of the broader frequency acquisition range than a conventional one the stability of the loop degrades appreciably when the input signal frequency is less than the nominal frequency of the digitally controlled oscillator. The system dynamics have been characterized by measuring the Lyapunov exponent and the correlation dimension. Further it has been shown that the stability range of a SLR-DPLL can be extended using a modified loop filter incorporating time delay feedback technique. The modified SLR-DPLL (MSLR-DPLL) with this additional derivative control along with the loop digital filter (LDF) shows faster convergence than the unmodified one for proper choice of system design parameters. Consequently, the MSLR-DPLL becomes more suitable for practical applications. [Copyright &y& Elsevier]

In this study, a fast and fully software‐based algorithm for digital phase‐locked loop (PLL) is proposed via a new hybrid approach in software and hardware by using an advanced digital signal processor architecture. The proposed algorithm is robust against line disturbances such as phase‐angle jump, voltage sag, third harmonic injection, multi‐zero crossing and step change in frequency at the input voltage. Performance and robustness of the proposed method are investigated through experimental studies. Furthermore, it is compared with three different PLL algorithms in detail to show its superiority over existing methods. [ABSTRACT FROM AUTHOR]

This paper introduces a novel architecture of digital PLL. The goal of this architecture is to reach low jitter, fractional operation, and FSK modulation capability with low architecture complexity for small area, low power, and minimal design effort. The architecture is based on the bang-bang phase detector, so that usage of time-to-digital-converter circuits is avoided, with no need for any background calibration. The key enabling blocks are a phase interpolator-based exact fractional frequency divider, and a multi-output bang-bang phase detector. The prototype implemented in 130 nm reaches 1-psrms absolute jitter while operating in integer mode and 1.9 psrms absolute jitter while operating in full fractional mode, with an output frequency of 1 GHz and reference frequency of 25 MHz, consuming 7.4 mW from a supply of 1.3 V. FSK modulation of the 1 GHz carrier up to 300 kbps with a frequency deviation of \pm150 kHz is also implemented and measured . [ABSTRACT FROM PUBLISHER]

This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm². The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 µW. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 µW (2.4 µW) under a supply voltage of 0.5 V (0.25 V). [ABSTRACT FROM AUTHOR]

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase‐locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm2. [ABSTRACT FROM AUTHOR]

A coarse–fine time-to-digital converter (TDC) is presented with a calibrated coarse stage followed by a stochastic fine stage. On power-up, a calibration algorithm based on a code density test is used to minimize nonlinearities in the coarse TDC. By using a balanced mean method, the number of registers required for the calibration algorithm is reduced by 30%. Based upon the coarse TDC output, the appropriate clock signals are multiplexed into the stochastic fine TDC. The TDC is incorporated into a 1.99–2.5-GHz digital phase-locked loop (DPLL) in 0.13-\mum CMOS. The DPLL consumes a total of 15.2 mW of which 4.4 mW are consumed in the TDC. Measurements show an in-band phase noise of -107 dBc/Hz which is equivalent to 4-ps TDC resolution, approximately an order of magnitude better than an inverter delay in this process technology. The integrated random jitter is 213 fs rms for a 2-GHz output carrier frequency with 700-kHz loop bandwidth. The calibration reduces worst-case spurs by 16~dB. [ABSTRACT FROM AUTHOR]

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9-7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations. [ABSTRACT FROM AUTHOR]

This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm^2 it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

A new three-phase digital phase-locked loop (DPLL) is proposed to determine the instantaneous grid frequency under power system disturbances. The proposed solution is based on single-phase DPLL algorithms, defining the estimated grid frequency as a nonlinear weighted mean of the three single-phase DPLL outputs. Orthogonal signals required by the DPLL algorithms are obtained through a fictitious quadrature voltage using five different appropriated approaches. The proposed structures have been assessed through extensive analysis under balanced and unbalanced conditions. For this purpose, real voltage dips collected in a Spanish wind farm along several months are included in the paper as examples of frequency estimations. In addition, results from conventional three-phase DPLL topologies are presented to confirm the validity of the proposed DPLL structures. [ABSTRACT FROM AUTHOR]

This article investigates the effect of the conventional and extended time-delayed feedback control techniques of chaos control on a first-order positive zero-crossing digital phase locked loop (ZC1-DPLL) using local stability analysis, two-parameter bifurcation studies and two-parameter Lyapunov exponent spectrum. Starting from the nonlinear dynamics of a ZC1-DPLL, we at first explore the time-delayed feedback control (TDFC) algorithm on a ZC1-DPLL in the parameter space. A condition for the optimum value of the system control parameter is derived analytically for a TDFC based ZC1-DPLL. Next, the extended time-delayed feedback control (ETDFC) technique on a ZC1-DPLL is described. It is observed that the application of the delayed feedback control (DFC) technique on the sampled values of the incoming signal inside the loop finally results in the nonlinear DFC of the phase error dynamics. We prove that, for some suitably chosen control parameters, an ETDFC based ZC1-DPLL has a broader stability zone in comparison with a ZC1-DPLL and its TDFC version. [ABSTRACT FROM AUTHOR]

This paper identifies the unavoidable time skew between counter and TDC inputs, if not properly compensated or corrected, as the major source of spurs in the output spectrum of an All-Digital-Phase-Locked Loops (ADPLLs). The frequency and the level of the main spur induced by the time skew are first analytically estimated. Then, an ADPLL, operating in the 3-4-GHz band, is designed in 90-nm CMOS technology and the reported simulations confirm the theoretical results. A simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts is proposed. The glitch corrector is demonstrated to cancel out the −24-dBc spur and its harmonics, without altering the lock transient behavior of the ADPLL. [ABSTRACT FROM AUTHOR]

Applying gear shifting algorithms to the implementation of Phase Locked Loops (PLLs) can significantly improve their performances. However, the behaviors of gear shifting digital PLLs (GSDPLLs) have not been fully studied due to the existence of newly adaptive control parameters. These parameters play a very important role in the design of GSDPLLs. In this paper, various nonlinear behaviors of GSDPLLs including the steady state periodic behaviors, divergent behaviors and chaotic behaviors, are studied. In particular, the effects of the initial conditions of GSDPLLs on their dynamical behaviors are investigated. The obtained results are useful for the design of GSDPLLs. Numerical simulation results are presented for illustrations. [ABSTRACT FROM AUTHOR]

SUMMARY In contrast with the conventional split loop digital phase lock loop, a new loop is presented in this paper that differs from the earlier version principally by design aspects. It incorporates an additional phase modulation input along with its frequency modulation input in the digital controlled oscillator. It is capable of eliminating the deleterious effects of rounding and truncation error with faster signal accusation. Higher loop stability is also achievable using the new split loop digital phase lock loop. Furthermore, radio frequency filtering is done using an In phase and Quadrature phase (IQ) voltage controlled oscillator to avoid interaction between the loop filter and the radio frequency filter. Copyright © 2011 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Abstract: A repetitive-Fuzzy PID and digital phase-locked loop (DPLL) integrating control strategy for High-Frequency(HF) inverter power supply is presented. The power modulation of HF-Inverter used repetitive-Fuzzy PID compound control,which can enhance the ability of the control system to withstand the parameter variations and nonlinear uncertain disturbances, and improve the dynamic characteristic of the control system; the DPLL was applied.to control the output frequency of HF-inverter,which reduce the losses of switching components and improve the efficiency of the power system. The experimental results show that the proposed control scheme can endow the HFinverter power supply with good steady state and dynamic performance and the power modulation control system can keep better precise control quality, high output power factor and verify the validity of the proposed integrated control strategy. [Copyright &y& Elsevier]

The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency. [ABSTRACT FROM AUTHOR]

The paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different subblocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed. Digital and All Digital PLLs are gaining popularity because of their ease of implementation in FPGA's and ASIC's. [ABSTRACT FROM AUTHOR]

A spur reduction technique in fractional‐N phase‐locked loops based on a current‐mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45° offset in each quadrant, and this non‐linear property leads to fractional spurs. The proposed 45° phase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement. [ABSTRACT FROM AUTHOR]

A near‐threshold all‐digital phase‐locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near‐threshold condition from 0.52 to 0.58 V VDD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V VDD, a lock‐in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to event‐driven or low‐voltage applications. [ABSTRACT FROM AUTHOR]

Time synchronization is one of the most fundamental services for numerous wireless sensor network applications. In this article the definition and basic concepts of time synchronization are introduced, and the related work is summarized in brief. Through analyzing the characteristics of the existing typical synchronization protocols and making a comprehensive comparison of the performance of various algorithms, we present a common guideline for designing the time synchronization protocol in WSN. Following this guideline, we develop a new time synchronization protocol called Self-Correcting Time Synchronization (SCTS), which converts the time synchronization problem into an online dynamic self-adjusting optimizing process to make the offset compensation and drift compensation simultaneously. The time and space complexities of the algorithm implementation are very low. In addition, the SCTS protocol fully exploits the inherent broadcast property of wireless channel, so the communication overhead is rather low. Because the algorithm implementation is based on the phase locked loop principle, an equivalent digital PLL without an actual voltage controlled oscillator is also proposed to avoid introducing the extra hardware required by a traditional PLL circuit. Finally, we validate SCTS on the Berkeley Mica2 experimental platform, and the performance is evaluated and compared to the existing typical time synchronization protocol. [ABSTRACT FROM PUBLISHER]

An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25 °C, and 90 MHz to 1.2 GHz at 0.5 V and 100°C. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 Ps rms. The phase noise under nominal operating conditions is -112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 μm x 150 μm. [ABSTRACT FROM AUTHOR]

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at high-level design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock sub-system and the total system power budget is assessed. [ABSTRACT FROM PUBLISHER]

In digital phase‐locked loops (PLLs), the finite resolution of digital representation (quantisation) could pose problems, including jitter peaking and limit‐cycle behaviour; both could ruin the frequency stability of a PLL. The resolution of the digitally controlled oscillator (DCO) in the PLL is limited by the smallest dimension available in a given process technology. Currently, one resorts to exhaustive time‐domain simulations to ensure correct operation of a PLL. Using a behavioural model of a PLL as verification, how to choose the DCO resolution without resorting to time‐domain simulations is investigated. The conditions on signal statistics for correct behaviour are repeated and the analysis to estimate the required resolution is provided. As it turns out, the root‐mean‐square value of the frequency deviation – neglecting quantisation – is the coarsest possible DCO resolution. One can estimate this value accurately by the integration of its power‐spectral density, derived from the well‐known phase‐domain model of a PLL. [ABSTRACT FROM AUTHOR]

This Letter presents an 8‐bit fractional frequency divider by utilising current‐mode phase interpolator (PI) for digital phase‐locked loops. A novel track‐and‐hold circuitry is proposed between the PI and divide‐by‐2. It can remove the glitches generated by the current‐interpolation structure. This method also relaxes the requirement of the minimum input frequency, while maintaining the same output frequency. The proposed fractional frequency divider is designed and fabricated with a 65‐nm CMOS technology. It dissipates a DC power of 0.8 mW from a 1.2 V supply. The measurement result shows that the fractional frequency divider achieves an uncalibrated in‐band spur of −43 dBc. [ABSTRACT FROM AUTHOR]

Bang‐bang phase‐locked loops (PLLs) are prone to generate unwanted output spur tones and high noise floor. In this reported work, a spur reduction technique based on dithering is compared to an alternative technique which exploits oscillator intrinsic noise. It is shown how the latter, joined to a proper loop design, allows eliminating unwanted spur tones while yielding a lower noise floor. [ABSTRACT FROM AUTHOR]

We present a radio-frequency (RF) signal distribution system via optical fibers. We utilize an all-digital platform that encompasses a phase-locked loop, numerically-controlled oscillator, and fiber phase noise cancellation system. Our system achieves a fractional frequency transfer stability of 4 × 10-13 at 1 s and 6 × 10-17 at one day for the distribution of RF signals over 70 km of optical fiber. We demonstrate that this performance can be achieved with standard crystal oscillators. Our system is scalable, configurable, and flexible, allowing distribution of signals at different frequencies while maintaining over two orders of magnitude of the fiber phase noise suppression. [ABSTRACT FROM PUBLISHER]

Carrier phase synchronisation is essential for coherent communications. Receivers typically use digital phase-locked loops (DPLLs) to acquire the carrier phase. The lock range of DPLLs, i.e. the range of frequency offsets that they can acquire, is usually significantly less than the initial frequency uncertainty in typical systems. Hence, acquisition is achieved by sweeping through the frequency uncertainty range, and stopping the sweep when the DPLL acquires the signal. Since the transmitted data symbols are in general unknown, successful acquisition is determined by a non-data aided carrier lock detector (CLD). In this reported work, a maximum-likelihood based CLD is derived which has low implementation complexity, and is better than existing CLDs while being impervious to errors in the receive Automatic Gain Control (AGC). [ABSTRACT FROM AUTHOR]

Distribution of precise time signals among the nodes of a network is a fundamental requirement for digital transmission and switching systems in telecommunication and control. Cideciyan et al., (1987) conjectured that two-way master-slave (TWMS) networks present, in the general case, a better performance than one-way master-slave (OWMS) considering the long term linear master frequency drift. In this work we study the TWMS case using dynamical system theory showing that, due to the effects of long-term clock instabilities, the steady-state frequency-error is unstable for a number of slaves higher or equal than four, limiting the use of this kind of architecture. [ABSTRACT FROM PUBLISHER]

Convergence behavior of the previously proposed time-delay digital tanlock loop (TDTL) is analyzed. The approach is built on the actual number of steps required for the convergence of the phase error to its steady-state value. Unlike the first-order conventional digital tanlock loop (CDTL), the Lipschitz bound of TDTL is not a tight limit for the actual convergence time, especially for higher values of the absolute difference between the initial and the steady-state phase errors. For a frequency step input, the first-order TDTL locks faster than CDTL under suitable arrangement of the loop parameters [ABSTRACT FROM PUBLISHER]

The power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

A drifting model for the resonant frequency and retardation amplitude of a photo-elastic modulator (PEM) in the photo-elastic modulated Fourier transform spectrometer (PEM-FTs) is presented. A multi-parameter broadband-matching driving control method is proposed to improve the thermal stability of the PEM interferometer. The automatically frequency-modulated technology of the driving signal based on digital phase-locked technology is used to track the PEM’s changing resonant frequency. Simultaneously the maximum optical-path-difference of a laser’s interferogram is measured to adjust the amplitude of the PEM’s driving signal so that the spectral resolution is stable. In the experiment, the multi-parameter broadband-matching control method is applied to the driving control system of the PEM-FTs. Control of resonant frequency and retardation amplitude stabilizes the maximum optical-path-difference to approximately 236 μm and results in a spectral resolution of 42 cm−1. This corresponds to a relative error smaller than 2.16% (4.28 standard deviation). The experiment shows that the method can effectively stabilize the spectral resolution of the PEM-FTs. [ABSTRACT FROM AUTHOR]

A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 μm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24-1.68 GHz from a 1.2 V supply. [ABSTRACT FROM AUTHOR]