Search

In the paper, it is stated that the HfC x N 1-x coating was deposited by magnetron sputtering on the AISI 316L substrate materials at various substrate temperatures ( T s ). The results of XRD and TEM indicated that the HfC x N 1-x coatings were almost amorphous when the T s were below 400 °C, whereas the nanostructured Hf 2 CN was formed at the T s of 400 °C. The Hf 2 CN nanocrystalline formation resulted in a significant improvement in the mechanical properties of HfC x N 1-x coatings. The electrochemical tests demonstrated that the stable HfC x N 1-x coatings improved the corrosion resistance of the AISI 316L. The platelet adhesion tests and hemolysis ratio tests indicated that the HfC x N 1-x coatings presented an improved hemocompatibility when the T s varied from 25 °C to temperatures exceeding 300 °C, which might have occurred due to the surface topography, the interfacial tension and the γ s d / γ s p ratio.

In this paper, we propose a hierarchical test integration method for 3-D ICs. The method can handle a die with logic cores and memory cores. In addition to handle the test controlling of a hierarchical 3-D IC, furthermore, it also can support the test controlling of a 3-D IC with multiple towers. For a 3-D IC, the hierarchical test integration method uses two types of 1149.1-based test interfaces for the bottom die and nonbottom dies. Therefore, the test access ports for the two test interfaces are the same. Also, the number of required test pads of the proposed test interface is only 4. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing.

With the continuous running of the nuclear power plants, a great deal of unavailable spent fuel associated assemblies were and will be produced in the aggregates of the nuclear power plants, which are usually stored in the spent fuel storage pool and occupy lots of spent fuel storage racks, making the spent fuel storage facility of the nuclear power plants face the risk of being filled up. Therefore, it drives the nuclear power plants to seek a new method to increase the spent fuel storage capacity. In order to increase the storage capacity of the spent fuel storage racks, a shearing device is proposed to shear the rods and base plates (or spider assemblies) of the spent fuel associated assemblies, reducing the storage volume of the spent fuel associated assemblies and reducing the amount of the occupied spent fuel storage racks. The technology of water-hydraulic shear is applied to carry the shear process through underwater cold extrusion, effectively ensuring the integrity of the rod structure and avoiding the pollution caused by radioactive substances. Besides, no swarf would be produced to pollute the spent fuel storage pool. Through the finite element calculation and confirmation on the spot, it is verified that the bearing requirement of the fixed blade (the key assembly unit) of the shearing device is met during the relevant disassembling process. Currently, the shearing device has been successfully applied to reducing the storage volume of the spent fuel associated assemblies in LingAo Nuclear Power Plant. Therefore, the shearing device is of certain promoting and reference value.

In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/microbump fault tolerance scheme to resolve this issue. First, we use a fast heuristic to predict the worst IR-drop distribution under a given faulty rate by analyzing power simulation results. Next, we use an incremental repair method to enhance power delivery network until reaching the given target IR-drop. The experimental results show that our methodology is effective in power delivery network enhancement in TSV/microbump DFM.

This paper proposes a resilient Time-to-Digital Converter (TDC) that lends itself to cell-based design automation. We adopt a shrinking-based architecture with a number of distinctive techniques. First of all, a specialized on-chip re-calibration scheme is developed so that the real-time transfer function of the TDC in silicon (which maps an input pulse-width to its corresponding output code) can be derived on the chip and thereby the absolute value (instead of just a relative code) of an input pulse-width under measurement can be reported. Secondly, the sampling errors stemming from the jitters of training clocks used in the calibration scheme are mitigated by the principle of multi sampling. Thirdly, a flexible coarse-shrinking block is adopted and an automatic adjustment scheme is employed so that the coarse-shrinking block can adjust itself when operated under different input pulse-width ranges.

Three dimensional IC (3DIC) is becoming practical in today's consumer electronics designs. However, one major problem remains in design synthesis and flow: how to model heterogeneous die(s) with major logic die for power synthesis and signoff. This work provides a realistic model and principle for heterogeneous dies power network for 3DICs. It is based on given abstract or early stage information like bump location and power consumption from the provider. Our work also uses this model to synthesize power network with bottom logic die in the design flow. The result is DRC clean power network without IR and EM violation for all power domains. First, we analyze the location and power consumption of power bump for heterogeneous die(s). Second, according to previous analysis, we decide the stripe location and power sink location of heterogeneous dies model by a clustering method. After the initial model is synthesized, we convert it to a node graph with corresponding resistance of via and metal layer, also nodal voltages. Third, the model is optimized by using Sequential Linear Programming (SLP) to adjust stripe width. It will improve the model iteratively until the target IR-Drop is met. Furthermore, our work will create a pseudo DEF of the proposed model to be incorporated with the commercial tool for verification. We experiment on a real case from design house containing a 3D DRAM stack to demonstrate the effectiveness of this cross-layer realization. Results show that we can save 34% metal layer usage in one of the power domains in our case by using proposed methodology.

DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization. Through proper design abstraction, our component-based modeling approach provides increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation. We validate the accuracy of DArT with respect to the physical layout and circuit simulation of an industrial 68 nm commodity DRAM device as a reference. The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.

3-D integration has been touted as an approach to reducing the lengths of critical paths in field-programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and microbump misalignment. Testing the interconnection faults becomes inevitable. In this paper, we present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. The experimental results show that 12 test patterns (TPs) suffice to achieve 100% open fault coverage (FC). To detect all possible neighboring short faults, we need more than 40 TPs, whose number increases only slightly with the height of the 3-D FPGA. The TPs have high delay FC (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50 × 50 × 2 to 50 × 50 × 6, demonstrating the scalability of our method.

With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to repair functional faults caused by defects. Spare bits with logical reconfiguration mechanism are used to replace data retention faults caused by process variation. Also, a diagnosis algorithm is proposed to identify data retention faults. Simulation results show that the proposed BISR scheme for a DRAM with 2 spare rows, 2 spare columns, and 8 spare bits can provide higher repair yield than a BISR scheme for a DRAM with 3 spare rows and 3 spare columns.

Memory, especially DRAM, is one of the candidates to be considered in three-dimensional integrated circuit (3-D IC), and in particular, to be heterogeneously stacked with a system on chip (SOC) for mobile applications. Even though the memory is tested and repaired beforehand, the known good die (KGD) can become bad during the integration process. Traditional schemes may not be able to redo the repair and obtain a known good stack (KGS), let alone unused spares be reused. We propose an off-chip repair scheme to deal with the inaccessibility from outside of the memory die. Using a through silicon via (TSV) to access the redundancy control circuit (RCC), we reactivate the unused spares by overwriting their states as if the corresponding fuses are blown. Even when the row or column, which has already been repaired, is damaged again, we are able to replace it with a new spare. Our simulation using a 65 nm process technology shows that the maximum timing penalty of the off-chip repair is only 93ps, compared to the on-chip method. The area overhead is estimated to be 490 μm2 per fuse set by using a 5 μm diameter TSV process. Most importantly, the yield improvement of a two-die stacked memory can be over 50% with yield excursion reduced to 8%.

A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt–Trigger inverter, the parametric delay fault on the TSV can be characterized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32768 TSVs when the test clock is running at 10 MHz.

This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-DLL) and a Dual Locking Mechanism (DLM), this method can be used to maintain a global clock signal between two dies in a 3-D IC, and thereby enabling the synchronous 3-D IC design methodology. Unlike previous designs, ours does not need to replicate the delay of the inter-die clock wire. This property can make our scheme more adaptive to various 3-D technologies and more robust to PVT variation. Such a method has several other benefits. For example, it can accommodate the ever-increasing process variation easily through its silicon tracking ability. Simulation results indicate that it can support clock signals running up to 2.8 GHz. Silicon measurements of a test chip in a 90 nm CMOS technology show that the phase error can be locked constantly to less than 9.6 ps at a clock frequency of 600 MHz, with a peak-to-peak jitter of 9.778 ps and a power consumption of only 1.8 mW.

In this paper, we propose a method and the required architecture for characterizing the propagation delays of the through Silicon vias (TSVs) in a 3-D IC. First of all, every two TSVs are paired up to form an oscillation ring with some peripheral circuits. Their joint performance can thus be measured roughly by the oscillation period of the ring. Next, we utilize a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in an oscillation ring-a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring's period. By some following analysis, the propagation delay of each TSV can be revealed. On top of scheme, we also present an architecture that can activate the performance characterization process of each test unit - that consists of two TSVs - one at a time in a proper sequence. The area overhead is only 18.97 equivalent two-input NAND gate per TSV, by which one can gain the ability to profile the capacitances and the propagation delays of the TSVs on a 3-D IC.

Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.

Crowbar conduction has an impact on the transient characteristics of a doubly fed induction generator (DFIG) in the short-circuit fault condition. But crowbar protection is seldom considered in the aggregation method for equivalent modeling of DFIG-based wind power plants (WPPs). In this paper, the relationship between the growth of postfault rotor current and the amplitude of the terminal voltage dip is studied by analyzing the rotor current characteristics of a DFIG during the fault process. Then, a terminal voltage dip criterion which can identify crowbar conduction is proposed. Considering the different grid connection structures for single DFIG and WPP, the criterion is revised and the crowbar conduction is judged depending on the revised criterion. Furthermore, an aggregation model of the WPP is established based on the division principle of crowbar conduction. Finally, the proposed equivalent WPP is simulated on a DIgSILENT PowerFactory platform and the results are compared with those of the traditional equivalent WPPs and the detailed WPP. The simulation results show the effectiveness of the method for equivalent modeling of DFIG-based WPP when crowbar protection is also taken into account.

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.

3-D integration provides a means to overcome the difficulties in design and manufacturing of system-on-chip (SOC) and memory products. Introducing a short vertical interconnect, called through-silicon via (TSV), makes it feasible to repair and recycle bad dies by stacking. We propose a method to accomplish this using a dual-TSV hardwired switch (DTHS) in which the via-hole location is programmable. With the DTHS, we activate a spare and establish inter-die routing. The spare is nothing but a good part in another bad die. To be 3-D reparable, the design is partitioned into disjoint parts. The effort for the modification is minor in view of that a typical SOC is readily composed of modules with predefined functions and supply voltages. The DTHS is used: 1) to shut off power connections of both failed and unused parts; 2) to disconnect their signal paths; and 3) to redirect them to the selected good parts in the stacked dies. Despite the speed is degraded due to the extra load incurred by the DTHS, our simulation shows that the increase in delay time can be limited below 100 ps with an over-designed buffer which occupies 0.8% of the area of a 30 μm TSV, using a 65-nm CMOS process. The performance degradation turns out to be a necessary evil, since the increased height of the die stack leads to a thermal conductivity poorer than its 2-D counterpart. The 3-D patch die helps to shorten time-to-market and turn the irreparable dies profitable.

Tests on rolling technology of four-graded RCC were carried out on dam site and then recommended construction parameters of four-graded RCC was proposed, which aimed to provide technique support for application of four-graded RCC in hydropower projects. Results show that when water consumption is 71kg/m3 and VC value is 3s~5s of four-graded RCC, large aggregates are coated with mortar sufficiently and the mixture has good performance of being-rolled and anti-separation. Recommended parameters of four-graded RCC are as follows: 2 times without vibration＋6 times with vibration＋2 times without vibration for 0.4m-thick layer, 2 times without vibration＋8 times with vibration＋2 times without vibration for 0.5m-thick layer, with rolling exciting force 395kN and walking speed 1.0~1.5km/h. Then the relative compaction of four-graded RCC can reach or exceed 98.0%.

A latent defect in a power-delivery TSVs in a 3D IC could cause power glitches under a heavy workload in the field and thereby leading to timing failure. In order to catch these defects before they actually strikes, on-line ring-oscillator based VDD-drop monitoring schemes have been proposed previously. However, these methods have not taken into account the effect of the temperature, which could affect their accuracy in the final VDD prediction. In this paper, we present a temperature-aware test method for power-delivery TSVs, with several features - including a process-calibration scheme and a temperature-aware worst-case VDD prediction scheme. Based on the these schemes, the pass-or-fail decision on the quality of a power-TSV can be made more accurately.

Many TSVs in a 3D IC are not used for signal transmission but for power delivery. Techniques needed to detect them have not been studied in-depth in the literature. In this paper, we present a test method for power-delivery TSVs, by embedding ring-oscillator (RO) based monitors (in a scalable architecture) to detect if there is any excessive voltage-drop at the end of any TSV during a manufacturing test session. One key feature as opposed to previous RO-based methods is that our approach is able to detect the worst-case dynamic voltage-drop (occurring in a very short period of time such as 1ns), rather than just the average voltage-drop over a long period of time. This is essential in order to detect small defects inside the power delivery network. These defects, if not detected, could set off a transient timing failure when the IC is operated in a system.

Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and

Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.

Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers to fit the number of stacked 3D DRAM dies such that the IO-channel power can be minimized. A BIST design supporting specific test patterns and test flow for the driver tuning is proposed as well. Simulation results show that about 6.16×10 -- 2 J energy saving can be achieved for a logic-DRAM stack with 150fF/die TSV load under 100s write operations if the proposed BIST-assisted tuning scheme is implemented in the logic die.

The analog built-in self-test (BIST) scheme, with stimulus generation and response extraction based on the /spl Sigma/-/spl Delta/ modulation, is proven to be quite effective for sampled-data systems. We show that the /spl Sigma/-/spl Delta/ modulators can be selected optimally for certain applications and functional tests. The criteria for valid tests are also derived. In particular, a valid frequency response test is determined by the frequency response observation range FROR/sub BIST/(z) of the BIST circuit. Given the transfer function H/sub CUT/(z) of the circuit under test, the requirement becomes FROR/sub BIST/(z)/spl Gt/|1/H/sub CUT/(z)|. Using the MOSIS 0.35-/spl mu/m CMOS process, we have implemented a test chip containing a Fleischer-Laker biquadratic low-pass filter as the circuit under test. An on-chip one-bit digital-to-analog converter provides the analog stimulus from a bit stream which is applied externally. For each test item, different bit streams, synthesized by first-, second-, and fourth-order /spl Sigma/-/spl Delta/ modulators that are programmed by software, are compared for performance. First- and second-order /spl Sigma/-/spl Delta/ modulators are implemented on the test chip as the candidates for the analog response extractor. The measurement results by single-tone tests and multitone tests validate the feasibility of the BIST scheme.

PDN evaluation/synthesis techniques have been used to facilitate the planning/construction of PDNs in integrated circuits at early physical implementation stages. They are rarely relevant after the routing stage when few routing resources are left and hence call for a repair strategy. The reason is that the traditional methods often apply wire widening or wire density increment directly without taking signal routing into account. Moreover, intuitively adding connections to the PDNs using the entire space available is quite time-consuming and eventually leads to lack of routing resources for later design ECO. Therefore, in this paper, we propose an approach to efficiently repairing the PDNs at the signoff stage. The greedy-Pareto-optimal (GPO) method is used to select the most effective regions to enhance the power rail connectivity. Maximizing the IR-drop improvement and minimizing the use of routing resources are considered at the same time. The method has been incorporated in our backend design flow and verified by leveraging a commercial P&R tool. On a test case of image signal processor, the experimental results show that the proposed PDN ECO approach can improve the worst IR-drop from 9.34% to 3.84% (i.e., 58.9% improvement) in the post-routing stage, where the ECO wire pitch is 3.5 times the minimal routing pitch.

As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficiently utilize a given area. Different types of test structures with three-level interconnects are developed and validated using a novel simulation system. Based on the proposed algorithm, single and multiple defects can be detected and identified precisely without ambiguity. The methodology standardizes the design of test structures for defect capturing as well as their usage within a common pad frame, which can be shared for various processes and applications. A test chip of 22/spl times/6.6 mm/sup 2/ containing a variety of types of these test structures was implemented to demonstrate the design feasibility.

Honeycomb and diamond networks have been proposed as alternatives to mesh and torus architectures for parallel processing. When wraparound links are included in honeycomb and diamond networks, the resulting structures can be viewed as having been derived via a systematic pruning scheme applied to the links of 2D and 3D tori, respectively. The removal of links, which is performed along a diagonal pruning direction, preserves the network's node-symmetry and diameter, while reducing its implementation complexity and VLSI layout area. In this paper, we prove that honeycomb and diamond networks are special subgraphs of complete 2D and 3D tori, respectively, and show this viewpoint to hold important implications for their physical layouts and routing schemes. Because pruning reduces the node degree without increasing the network diameter, the pruned networks have an advantage when the degree-diameter product is used as a figure of merit. Additionally, if the reduced node degree is used as an opportunity to increase the link bandwidths to equalize the costs of pruned and unpruned networks, a gain in communication performance may result.

IR-drop monitoring has been an effective means to assess the power integrity in real silicon. Existing methods, however, fail to achieve a high accuracy and a high sampling rate simultaneously. In this paper, we present a novel method to resolve this dilemma. First of all, we focus on the measurement of the worst-case IR-drop, instead of the entire sampled VDD waveform. This strategy can make a high sampling rate easily viable. Secondly, we perform periodic calibration to account for not only the process variation but also the temperature change. Post-layout simulation indicates that this method can support 1 GHz sample rate while keeping the measurement error less than 4.81 mV at the same time.

Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

Even though three-dimensional integrated circuits (3-D ICs) with through silicon vias (TSVs) potentially provide modern electronic devices with various advantages, current commercial tools do not realize their layout as a whole, but one by one in a stack of dies. The capability of inter-die co-optimization remains largely restricted. This is, in part, due to that the tools draw heavily on 2-D IC's design and implementation styles. Inter-die co-optimization is imperative for 3-D ICs where timing, power, and area are simultaneously considered. In this paper, we show how to enable inter-die co-optimization with adaptive buffering. Empirical results indicate that the proposed scheme eliminates iterative routines, which can help hasten the pace of realizing 3-D integration.

Three-dimensional (3D) integration using through silicon via (TSV) is a promising approach to coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented by stacking multiple dies which are vertically connected by TSVs. This may shorten the global interconnects of a 3D IC and greatly improve its performance and power consumption. High bandwidth is achieved by the increase of IO channels provided by the TSVs, which also reduce the unnecessary waste of energy during data movement. In addition, the 3D integration technology shows other advantages over 2D technology, such as high functionality, heterogeneous integration, small form factor, etc. However, there are still challenges that need to be tackled before volume production of 3D ICs using TSV becomes possible, including technology scalability, quality and reliability, yield, thermal management, equipment and infrastructure, and costs. To demonstrate the feasibility of 3D-IC technologies, many academic and industrial institutes have been working on various test vehicles, especially in recent years. An increasing attention also has been attracted around the world in the semiconductor industry by the development of related technologies. In this special session, we will discuss the evolutionary efforts toward the realization of 3-D ICs. As memory dies need to be integrated in most 3D-IC system, we will also address the challenges in the design and test of 3D memories against cross-layer process, voltage and temperature variations while suppressing thermal effect and power consumption, etc. We will share our experiences and show results from some of the test vehicles we have worked on, including processor/memory stacks, analog/logic stacks, logic/logic stacks, etc. We will show a 1,024-bit wide bus chip-to-chip interconnection using 40×40 fine-pitch TSVs to demonstrate ultra-low-power operation. For memories, we will present a 3D-RAM structure using small voltage-swing TSVs, vertical-device-stacking nonvolatile-SRAM and ReRAM, and a 3D vertical-gate NAND flash. To address the challenge of reliability and yield, we will also discuss important test techniques. Demonstration of benefits provided by 3D integration technology will also be shown. Last but not least, we will describe our development plan regarding various types of die stacking using heterogeneous process integration, especially processor/memory stacking that is widely believed to be a key technology in future generations of smart handheld devices.

Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization mechanism is also proposed to synchronize the BIST circuits in different dies. Furthermore, the BIST circuit provides the high-programmability feature to support the selection of RAMs in a die for testing such that it can support thermal management during the test. We design the proposed BIST scheme in a 3D IC with processor and RAM dies. Experimental results show that the area cost of the BIST circuit is very small. The area overhead of the BIST circuit for four 8192×64-bit RAMs in a die is only 0.45% using TSMC 90nm 1P9M CMOS process technology.

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.

In this paper, a bit weight extraction technique is proposed to test and calibrate the successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique is based on major carrier transition (MCT) testing, the MCTs are generated through simple capacitor switching and then measured by the embedded comparator and a coarse design-for-test (DfT) digital-to-analog converter (DAC) that couples to the capacitor DAC (CDAC). From the results, the individual bit weights are extracted and the ADC performance can thus be estimated and calibrated. Simulation results show very high test accuracy and linearity improvement can be achieved by the proposed technique.

Modern mobile device possesses function-rich, small, thin, low-power features. The electronics industry aggressively seeks possible solutions to achieve these demands. Among different techniques, 3-D integration can effectively provide such kind of advantages. However, to successfully accomplish vertical stacking, readiness of design toolset is one of the most important keys. In this paper, we present the challenges and state-of-the-art features of 3-D EDA tool chain. We introduce the complete realization technologies of system integration with through-silicon via (TSV) using TSMC 90nm process. For optimization of system performance, we summarize the stacking concerns for timing constraints due to various stacking applications. With the configurations, an approach is proposed to overcome 3-D timing optimization problem because commercial tool tackles only one die at one time. Empirical results show the approach is promising for present 3-D centric design methodologies.

3D ICs based on Through-Silicon-Vias (TSVs) enable the stacking of logic and memory dies to manufacture chips with higher performance, lower power, and smaller form factor. To improve the yield of the memory dies in 3D ICs, this paper proposes aBuilt-In Self-Repair (BISR) architecture which allows the sharing of spares between different layers of dies. The corresponding pre-bond (before the memory dies are bonded together) and post-bond (after the memory dies are bonded together) test flow is presented as well. In order to maximize the yield gain introduced by the cross-die spares, a die matching algorithm is proposed to determine which dies should be stacked together, so that the spare sharing can be most ef~cient. Experimental results show that the area overhead of the proposed BISR circuit is only 2.43%, which can be smaller if larger logic and memory dies are adopted, and the yield gain achieved by cross-die spare sharing can be up to 23%.

Power supply noise has become one of the primary concerns in low power designs. To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all possible scenarios. Since it is very difficult to capture the exact worst corner among the mist of complex functionalities in modern VLSI designs, statistical design methodologies have been adapted, which may bring significant design overhead. In view of this, various runtime techniques have been proposed in literature to suppress power grid noise adaptively. This paper first presents various challenges in power grid designs from an industrial perspective, explains the difficulties in handling them at deign time, and then reviews various runtime techniques to adaptively suppress power supply noise, including sensor-based power gating, re-routable decaps, proactive clock frequency actuator, and PLL based clocking.

We present a three-dimensional (3-D) CMOS imager to be used as a process development vehicle for through-silicon stacking. The 3-D CMOS imager comprises three tiers: CMOS image sensor (CIS), analog-to-digital converter (ADC), and image signal processor (ISP), all in a form of array implementation. The CIS tier contains a 2048 × 1536 backside illuminated pixel array, the ADC tier contains a 16 × 8 successive approximation register (SAR) ADC array, and the ISP tier contains a 4 × 2 parallel architecture core (PAC) array. The die stack employs both face-to-face and face-to-back bonding schemes. TSMC 0.18 μm 1P6M CIS process is used for device wafers; through-silicon via (TSV), formed after CMOS and from the front side of the wafer, is used for the post-foundry process performed at ITRI. The TSV diameter is 30 μm and the micro-bump pitch is 60 μm The target substrate thickness of the wafer varies from 5 μm for the CIS tier, 50 μm for the ADC tier, to 725 μm for the ISP tier.

Inverters with distributed storage(DS) play a very important role in a microgrid. A new kind of inverter called virtual synchronous generator(VSG) is proposed in this paper to emulate the behavior of synchronous generator(SG) in the utility. The core algorithm of VSG is to employ an electromechanical transient mathematic model of round SG. There are two important operation modes in microgrid: active power/reactive power control (PQ control) and voltage/frequency control(Vf control). So a governor and an excitation controller are developed to fulfill these two functions. If Vf control is selected in islanded operation, the objective of governor is to keep frequency in an acceptable range by adjusting the input active power to match the output power. The excitation controller is to maintain the output voltage of VSG by controlling the excitation current; If PQ mode is selected in grid-connected mode, active power could follow the dispatch command very well by the governor. But a Q controller should be developed to control the reactive power by adjusting the voltage reference of excitation controller. Additionally, two kinds of PQ control are discussed here: (1) unit output power flow control (UPC) and (2) feeder power flow control (FFC). Finally, the proposed algorithm and control methods are verified by a single VSG experiment.

This paper presents pre/post-bond testing and calibration techniques for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The underlying idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of its digital-to-analog converter (DAC) capacitor array (C-Array). During the pre-bond stage, when access to the die is very limited, we propose a calibration-oriented testing technique that only determines whether the ADC array can achieve the desired performance after calibration. Then, during the post-bond stage, we utilize the digital resources from the image signal processor (ISP) die to perform more thorough characterization and calibration of the ADC array. Simulation results are presented to validate the proposed techniques.

This paper presents a low-cost pre- and post-bond self-testing and calibration methodology for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The basic idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of the internal digital-to-analog converter (DAC) capacitor array. During the pre-bond stage, when access to the die is very limited, we propose a calibration-oriented testing technique that only determines whether the ADC array can achieve the desired performance after calibration. This substantially reduces the required design-for-test (DfT) circuitry complexity and test time. Then, during the post-bond stage, more thorough characterization on the ADC array is performed, we utilize digital resources from the image signal processor (ISP) die to analyze the measurement results, compute the calibration parameters, and perform the digital calibration. Simulation results are presented to validate the proposed techniques.

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18µm CMOS technology for a 16×32 TSV array in which each TSV cell size is 45µm2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.

A high-resolution all-digital duty-cycle corrector (ADDCC) with a novel pulse-width detector in cell-based design is presented. This work provides a wider acceptable duty-cycle range from 10% to 90% and a larger operation frequency range from 100MHz to 3.6GHz. We rely on an “Exponentially Segmented Binary Search” method for increasing the locking speed. Based on three types of circuit elements - Expand Element, Shrink Element, and Fine-Tuning Element, the clock's pulse width could be controlled accurately by a resolution as low as 2.8ps, and thereby achieving 50% duty-cycle within less than ±0.5% error in SPICE simulation. This proposed DCC, equipped with a new Pulse-Width Detector which can not only detect 50% duty-cycle precisely but also dynamically track the variation in operating conditions. A test chip has been taped out to validate this design. The simulation results in a 90nm CMOS process at 1V indicate that the peak-to-peak jitter is 6.2ps at 2GHz and the power consumption is 3.8mW.

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC’99 b19 benchmark is only about 0.15%.

In this paper, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation test, in which two TSVs are connected with some peripheral circuit to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring – a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring’s period. By some following analysis, the propagation delay of each TSV can be revealed. Monte-Carlo analysis of a typical TSV with 30% process variation on transistors shows that the characterization error of this method is only 2.1% with the standard deviation of 8.1%.

In the past few years, we have witnessed the energy crisis and the financial tsunami that played an unwanted duo, changing the world in many aspects that affect most of us. Like many others, the semiconductor industry is trying to recover from the depression triggered by the duo. While companies are working hard in getting out of the slump, many research organizations are rethinking how their R&D budget should be invested. We consider three-dimensional (3D) integration based on the through-silicon-via (TSV) technology a cost-effective way to explore new applications in the future, alleviating the fast growing development cost of system-on-chip (SOC) products. However, there are technical problems to be solved and business models to be established before the industry is ready for manufacturing TSV-based 3D integrated devices. In this paper, we will first give an overview of the status of the worldwide semiconductor industry, identifying challenges and trends, which somewhat justifies our focus on 3D integration. We will then discuss the design and test issues, and some solutions for 3D integrated devices. We will propose approaches from our work at ITRI and NTHU.

Since the penetration of wind power in electric power supply is increasing greatly, it is urgent to study the impact of wind power on the transient stability of electric power system. In this paper, a model for a simple electric power system with a large wind power plant is constructed, in which, a wind power plant which consists of 6 Doubly Fed Induction Generator (DFIG) transmits power to the system through two stages' transformation. The studies include examining the transient stability of the power plant in serious system fault under two operation strategies, i.e. fixed power factor operation and fixed voltage operation. The transient stability studies illustrate the reactive power control of DFIG could help maintain the voltage at the wind power plant during system voltage sag. However, once the DC voltage of DFIG reaches its limit, it is impossible for wind power plant to produce reactive for maintaining the voltage since the plant has to disconnect with the grid for purpose of protecting the wind turbines.

The choice of Doubly-fed induction generator (DFIG) operation strategy has a significant impact on voltage stability. Now there are two types including constant-power factor and constant-voltage control and their essential differences are different control strategies between the scheduling of reactive power and voltage control. The article presents control strategies of wind generator on two kinds of operation modes after establishing a simplified dynamic model of DFIG, and then utilizes static continuation power flow techniques (CPF), quasi-static time domain simulations (QTDS) and time domain simulations (TDS) to investigate their impacts on system stability. The simulation results show that both of control modes can maintain system voltage within a limited range in the changing process of wind power penetration. In addition, due to taking full advantages of DFIG reactive power regulation function constant-voltage control has a greater advantage than constant-power factor control on improving the system voltage stability.