Hierarchical Test Integration Methodology for 3-D ICs

In this paper, we propose a hierarchical test integration method for 3-D ICs. The method can handle a die with logic cores and memory cores. In addition to handle the test controlling of a hierarchical 3-D IC, furthermore, it also can support the test controlling of a 3-D IC with multiple towers. For a 3-D IC, the hierarchical test integration method uses two types of 1149.1-based test interfaces for the bottom die and nonbottom dies. Therefore, the test access ports for the two test interfaces are the same. Also, the number of required test pads of the proposed test interface is only 4. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing.