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DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:1356-1369
- Publication Year :
- 2014
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2014.
-
Abstract
- DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization. Through proper design abstraction, our component-based modeling approach provides increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation. We validate the accuracy of DArT with respect to the physical layout and circuit simulation of an industrial 68 nm commodity DRAM device as a reference. The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.
- Subjects :
- Engineering
Dart
Hardware_MEMORYSTRUCTURES
business.industry
Interface (computing)
Reference design
Bandwidth (signal processing)
Computer Graphics and Computer-Aided Design
Porting
CAS latency
Embedded system
Component (UML)
Electrical and Electronic Engineering
business
computer
Software
Dram
computer.programming_language
Subjects
Details
- ISSN :
- 19374151 and 02780070
- Volume :
- 33
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Accession number :
- edsair.doi...........d91b89c875fec7f697a90f0f530067a7