A high-resolution all-digital duty-cycle corrector with a new pulse-width detector

A high-resolution all-digital duty-cycle corrector (ADDCC) with a novel pulse-width detector in cell-based design is presented. This work provides a wider acceptable duty-cycle range from 10% to 90% and a larger operation frequency range from 100MHz to 3.6GHz. We rely on an “Exponentially Segmented Binary Search” method for increasing the locking speed. Based on three types of circuit elements - Expand Element, Shrink Element, and Fine-Tuning Element, the clock's pulse width could be controlled accurately by a resolution as low as 2.8ps, and thereby achieving 50% duty-cycle within less than ±0.5% error in SPICE simulation. This proposed DCC, equipped with a new Pulse-Width Detector which can not only detect 50% duty-cycle precisely but also dynamically track the variation in operating conditions. A test chip has been taped out to validate this design. The simulation results in a 90nm CMOS process at 1V indicate that the peak-to-peak jitter is 6.2ps at 2GHz and the power consumption is 3.8mW.