23 results on '"Vandeweyer, T."'
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2. Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell
3. Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density
4. Advanced Cu interconnects using air gaps
5. In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers.
6. Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry.
7. A 400GHz fMAX fully self-aligned SiGe:C HBT architecture.
8. Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology.
9. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability.
10. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length.
11. Gatestacks for scalable high-performance FinFETs.
12. A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process.
13. Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency.
14. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques.
15. Air gap integration for the 45nm node and beyond.
16. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application.
17. Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application.
18. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout.
19. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography.
20. A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM.
21. A new complementary hetero-junction vertical Tunnel-FET integration scheme.
22. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation.
23. In-line metrology for characterization and control of extreme wafer thinning of bonded wafers.
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