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The conditions for the growth of n-type Ge layers with the parameters required to create a Ge-MISFET with an induced p-type channel using the hot wire chemical vapor deposition (HW CVD) method are determined. The conditions for deposition using electron beam deposition and subsequent annealing of the subgate high-k dielectric ZrO2:Y2O3 layers are optimized, allowing us to achieve a leakage current value of 5 × 10–6 A/cm2. For the developed device structure, some parameters of the Ge-MISFET are calculated, such as the channel length, maximum voltage between the sink and source, and breakdown voltage. [ABSTRACT FROM AUTHOR]

This work discusses a junction-less nanowire tunnel field effect transistor (JLN-TFET) that combines the advantages of a junction-less field effect transistor (JLFET) and a tunnel field effect transistor (TFET). With a hetero-structure device made of silicon (Si) and germanium (Ge), an amalgamation of gate engineering and channel engineering is investigated. To eliminate junctions in the structure, a uniformly high dosage of doping (1019cm-3) has been employed throughout. In contrast to the source work function, which is set at 5.93 eV, the gate work function is set at 4.5 eV. When compared to junction less nanowire tunnel FET (JLTFET), the modified gate-all-around hetero junction less nanowire tunnel field effect transistor (GAA-H-JLNTFET) performs better. The proposed structure GAA-H-JLNTFET exhibits the ON current (ION) 6.5 × 10−5µA/m, the off current (IOFF) measures 2.97 × 10−20µA/m, the subthreshold slope (SS) is 12mV/Dec, and ION/IOFFis ≈ 1015which makes them immune to short channel effect and suitable for low power application in Nano regime. Further, in this work, the proposed structure is utilized to implement the dielectric modulated low-power biosensor. The drain current is taken as the sensitivity parameter. Five different biomolecules sensitivity are measured and found better than the previous published results. For the simulation and analysis, the Silvaco Atlas 2D simulator with non-local band-to-band tunneling is used. [ABSTRACT FROM AUTHOR]

Among several types of innovative bio-sensing technologies, label free dielectric modulated field-effect transistor (DM-FET) based biosensors, stand out because of their appealing properties, including ultra-sensitivity detection, mass-production capacity, low-cost manufacturing, and batch testing facility. This work investigates the Dielectric Modulated Tunnel Field Effect Transistor (DM-TFET) biosensor for low power applications and performance characterization. ATLAS TCAD simulator tool from SILVACO is used to simulate and characterise the biosensor. In this work we proposed and compared three different types of double gate (DG) TFET based biosensors, i.e., both side cavity (DG_BSC_TFET), drain side cavity (DG_DSC_TFET) and full both side cavity (DG_FBSC_TFET). The proposed biosensors are differentiated on the basis of the exposed area to trap the biomolecules. In particular, we focused on the sensitivity and ambipolarity of tunnel field-effect sensors. Further, we analysed the effect of biosensor performance on sensing surface properties, including electric field strength, transfer characteristics, Ion/Ioff ratio, and various other related parameters. The critical difficulties of device design and practical limits have been addressed. The simulated results show that the ambipolar current sensitivity of the proposed structure shows comparative better results than other published data, and it is observed that the sensitivity of the DG-FBSC-TFET-based biosensor is twofold more than the DG_BSC_TFET and DG_DSC_TFET. Due to the higher surface to volume ratio in DG_FBSC_TFET, a greater number of biomolecules are immobilised on the surface of the biosensor, which makes it a capable candidate for future low power label free biosensors. [ABSTRACT FROM AUTHOR]

In this paper, N-type and P-Type low power SiGe Silicon on Insulator Vertical TFET (SOI-VTFETs) are designed and then their drain current is investigated. The designed structures are calibrated with the reported structures considering the same model's environment for the validation of the design. Here, several advantages of SOI have been incorporated so that the low-voltage with low power (LVLP) VLSI designs digital circuits can be easily realized. Gate staking of high k -dielectric (HfO2) material with SiO2 was used to prevent the loss of the Lattice misfit structure using the equivalent oxide thickness approach. The proposed device's highest ON current and largest ON/OFF current are claimed to be (3.62 × 10−4 A/m) and (1013), respectively. Then the designed device is used to implement the full adder and the Infinite Impulse Response (IIR) filters. It is found that the performance of IIR filters is much enhanced over Finite Impulse Response (FIR) filters to keep flat response for altogether trial rates. The total delay of the IIR decimation filter via Merged Delay Transformation (MDT) is 0.181 ns with a Power Delay Product (PDP) of 3.5767. The current method employs the Routh Hurwitz Array method's advantages to derive the reduced-order denominator polynomial, and the reduced order numerator is obtained based on the resultant denominator polynomial. This order reduction technique is incorporated to reduce the number of delay units of the IIR filter and modified architecture offering a PDP of 0.22563, with its flat response initiated by SOI VTFET. The current model is productive in lowering area, power consumption, and stability over a specific sample rate or frequency. [ABSTRACT FROM AUTHOR]

InGaAs/Ge complementary FinFET technology has been considered as an alternative channel material for CMOS technology, useful for next-generation digital VLSI circuits. The soft errors in these C-FinFETs are dominated by the ion strike at the InGaAs n-channel FinFET due to its high charge collection efficiency, low ionization energy and high mass density. In this paper, a physics-based model of single-event transients (SET) in an InGaAs FinFET is proposed which captures the dependence of device, radiation and circuit parameters on the transient current. The electrostatic potential and the drain current models are developed considering the additional electron density due to the ion strike in the InGaAs n-channel FinFET with high-k dielectric material as the oxide layer. The SET current obtained from the model is validated using TCAD simulations for different device dimensions, dielectric materials, linear energy transfer (LET), strike positions and voltage bias. The developed model is integrated into the Cadence circuit simulator, and the output voltage perturbations are analyzed for different load capacitances and LETs. [ABSTRACT FROM AUTHOR]

Nowadays, the junctionless (JL) multigate (MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are the pacesetter within the emerging nanodevices because of their improved gate controlling nature [J J Kim and K Roy, IEEE Trans. Electron Devices51(9), 1468 (2004)] at 20 nm channel node. Here multiple gates are simultaneously controlling the channel. On the other hand, the alignment of the top and bottom gates is a source of worry during fabrication since its effects are detrimental to the performance of the device. Furthermore, with multiple gate-designed DG MOSFETs, the problem of top-to-bottom gate alignment becomes highly significant for the performance of the device. This paper is about an N-doped SiGe DG-JL-MOSFET where a high electron mobility III–V compound GaSb is employed at the source regime. To generate more on-current and low leakage current, SiGe is used for the channel and the drain. Material having high permittivity (HfO2) is used as the gate oxide to enhance the gate controllability at the 20 nm channel node. In this work, the impact of gate misalignment on DC and RF properties of asymmetric double-gate junctionless (ADGJ) and symmetric double-gate junctionless (SDGJ) MOSFETs at 20 nm channel is studied using simulations. The influence of gate underlap and overlap on several DC and RF characteristics such as IdVg, IdVd, gm, gd, intrinsic gain, Cgs, Cgd and fT are discussed in this manuscript, and it is observed that the DG-JL-MOSFET shows a better response to DC and RF characteristics for 50% of the gate misalignment towards the source. In the proposed structure, an improvement in drain current is observed during the misalignment of the front gate towards the source. The value of Ion / Ioff is also more in the case of the proposed heterostructure device than the earlier Si-based JLFET. [ABSTRACT FROM AUTHOR]

In this paper a detailed investigation is carried out upon doping less tunnel field effect transistor (DLTFET) under symmetric and asymmetric conditions. For this purpose, a range for back gate metal work function (ɸBG) from 4.1 eV to 4.8 eV and the back gate oxide thickness (tox) from 3 to 6 nm have been considered by keeping the front gate work function (ɸFG) fixed with 4.5 eV and EOT (Equivalent oxide thickness) of 0.8 nm respectively. Analysis with respect to analog parameters such as transconductance (gm), total gate capacitance (Cgg) and cut-off frequency (fT) has been made and compared with the range of symmetric and asymmetric conditions. It is observed from simulation results that the DLTFET has an optimum performance at ɸBG of 4.5 eV and tox of 0.8 nm EOT. Later the device is then utilised to implement common source amplifier circuit. A range of variations with respect to load resistor (RL) and drain resistor (RD) were made to check for the circuit's performance at gain's perspective. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) analytical model for the subthreshold characteristics like Surface potential, threshold voltage, subthreshold current and swing of uniformly doped, high-k gate stack double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed in this paper. The minimum surface potential obtained by solving the 2D Poisson's equation using evanescent mode analysis has been utilized to model the threshold voltage, subthreshold current and subthreshold swing. The effects of various parameters on these parameters have also been presented. The results show excellent matching with the numerical simulation data obtained by ATLAS™, a 2D device simulator from SILVACO. [ABSTRACT FROM AUTHOR]

The channel modulated junctionless gate all around (CM-JL-GAA) MOSFET improves the SCE's with high graded doping of the channel region. Temperature effects on electrostatic and analog/RF performance of channel modulated junctionless gate all around (CM-JL-GAA) MOSFETs have been explored in this work throughout a temperature range of 200 K to 500 K. The channel length, gate oxide thickness, and gate oxide material of CM-JL-GAA MOSFET has been varied to understand the impact of process parameters on device performance using Silvaco 3D device simulator. The electrostatic and analog/RF parameters have been figure out for the specified temperature range with process parameter variation. When the temperature of CM-JL-GAA MOSFETs is increased from 200 K to 500 K, the analog/RF performance is marginally affected. The intrinsic gain (AV) is negligibly affected (~3 dB) with raised in temperature. The adoption of a high-k gate dielectric improves electrostatic performance such as DIBL, SS and Ion/Ioff and marginal deterioration in the analog/RF performance of CM-JL-GAA MOSFETs, according to this study. With temperature changes, the high-k dielectric has a minor impact on the analog/RF performance of CM-JL-GAA MOSFETs. Hence, the CM-JL-GAA MOSFETs device have better analog/RF performance at higher temperature with high-frequency applications. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed for a single gate tunnel FET, introduced with a highly doped pocket in the vicinity of the source-channel junction and the bottom oxide layer being distributed between SiO2 and a high-k material such as HfO2. Introduction of the pocket region modifies the energy band diagram of the device thereby augmenting the electron tunneling from the source valence band to the channel conduction band in the band to band tunneling (BTBT) process of conduction. The proposed model results into an improvement in the surface potential, electric field profile and finally in the on state current Ion. Comparison of surface potential, electric fields for various Vgs has been made. Comparisons of the surface potential for various pocket widths, with and without the pocket & with & without the high-k dielectric material have also been made to show improvements in the proposed structure. Finally, drain current is computed and a comparison is made with & without the high-k dielectric material used in buried oxide. [ABSTRACT FROM AUTHOR]

In this study, MIS structures In/Al2O3/InSb and In/SiOx/anodic oxide/InSb were characterized. The A2O3 insulator layer were formed by the atomic layer deposition method. For second sample, we applied combination of insulators, which include anodic oxide film and SiOx layer deposited by the resistive evaporation method. For both structures, we mapped a fixed charge and interface trap level over 2-inch InSb wafers. The average value of the fixed charge level, NF, for MIS-structures In/Al2O3/InSb and In/SiOx/anodic oxide/InSb were 1.4 × 1011 cm–2 and 2.9 × 1011 cm2, respectively. The spread of Dit values over the wafer in the In/Al2O3/InSb MIS structure did not exceed 9% that confirms feasibility Al2O3 insulators films deposited by ALD as a passivation coating for InSb-based photodiode arrays.. [ABSTRACT FROM AUTHOR]

In present days, the improved performance in nanoscale dimensions is of enormous need than conventional CMOS devices. This paper presents an insight into Trigate FinFET in 5 nm technology using ATLAS 2D simulator. The drain current model based on surface potential calculation is shown to study the performance of tri gate FinFET. The 2D Poisson's equation is solved for both the gates of tri gate FinFET which results in effects of gate voltage in performance parameters. Different high-K dielectric materials are used in the proposed device and corresponding parameters are calculated to study its behavior in drain current characteristics, electrical parameters, and analog parameters. The On current is increased by 150 % then the existing architectures. The net electric field is increased by a factor of 2. There is a significant increase in Transconductance of the device. The simulated models are verified using Silvaco TCAD in ATLAS simulator. [ABSTRACT FROM AUTHOR]

In this paper, the proposed design of H-shaped TFET has been discussed. This design is providing a high Ion/Ioff ratio with a better Ion. HfO2 is used for better tunnelling current. The controllability of gate voltage on the drain current improves as the gate area increases. We can obtain better outcomes for current in this design by altering the architecture. With this device, Different parameters such as unit parameter, analog parameter, and linearity parameter have been studied and investigated the output of the H-TFET. As unit parameters, the electric field, electric potential, energy band diagram, and non-local band-to-band tunnelling rate (BTBT) have all been observed. Second and third-order harmonics distortion (HD2, HD3), third-order current intercept point (IIP3), third-order intermodulation distortions (IMD3), and second and third-order voltage intercept point (VIP2, VIP3) are evaluated as linearity parameters that characterize the device's distortions and linearity. We obtained Ion =1.6x 10 − 4 A/μm,Ioff=2.1 x 10 − 19 A/μm, Ion/Ioff=7.6 x 10 14 ,threshold voltage Vt=0.3449 V. © 2017 ElsevierInc.Allrightsreserved. [ABSTRACT FROM AUTHOR]

This paper exemplifies an exhaustive, figurative and subjective study on the RF performance and DC characteristics analysis of an Underlapped Double-Gate (U-DG) AlGaN/GaN heterojunction-based MOS-HEMT device with Hafnium-based high-k dielectric gate material. This paper depicts the effect of gate length variations on the drain current (ID), the transconductance (gm), the transconductance generation factor (gm/ID) and the RF FOMs intrinsic capacitances (CGD, CGS and CGG), intrinsic resistances (RGD and RGS), cut-off frequency (fT) and maximum oscillation frequency (fMAX). This study reveals shortening of channel length leading to better gate controllability hence an overall superior analog and RF performance is achieved. The U-DG AlGaN/GaN based MOS-HEMT device of 100 nm channel length shows a better Power Output Efficiency (POE) of 33% in contrast to 31% and 23% for the 200 nm and 300 nm devices respectively. [ABSTRACT FROM AUTHOR]

Thin HfTiOx high-k gate dielectric (Ti ~26.6%) has been sputter-deposited on strained Si0.81Ge0.19 heterolayers. The energy band discontinuities and interface properties were studied using X-ray photoelectron spectroscopy. The conduction band offset, and valance band offset between HfTiOx and Si0.81Ge0.19 were found to be 1.34 and 2.52 eV, respectively. Further, temperature-dependent (300–500 K) current density–voltage measurements (J–V) were utilized to explore the underlying leakage current conduction mechanism. The conductive dislocation and emission barrier heights at the hetero-interface have also been extracted from temperature-dependent J–V measurement. The barrier height of 1.22 to 2.02 eV for Schottky emission and 0.76 to 1.26 eV for Poole–Frenkel emission were estimated at the hetero-interface. To better understand the conduction mechanism between the hetero-interface and temperature-dependent J–V, a calibrated TCAD simulation was carried out. [ABSTRACT FROM AUTHOR]

U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL). [ABSTRACT FROM AUTHOR]

The ultrahigh-frequency (from several GHz to THz) performance of a graphene nanoribbon field-effect transistor (GNRFET) is analyzed using a semiquantum analytical model. The results indicate that the use of a high-k gate dielectric layer to improve the performance also increases the parasitic internal fringe capacitance. This limits the operation of the GNRFET in the higher frequency range. Hence, a design for a GNRFET structure with a combination of different gate dielectric layers is proposed to minimize the effect of the parasitic capacitance. The calculations based on the model illustrate that the proposed device could be used for high-frequency applications even in the THz range without compromising the figures of merit. [ABSTRACT FROM AUTHOR]

This paper investigates a novel hetero dielectric buried oxide and gate dielectric based PNPN tunnel field effect transistor (HDB-HDG-PNPN-TFET) using 2-D simulation. The buried oxide (BOX) is formed by SiO2 below the channel and source, HfO2 beneath the drain region. The asymmetrical gate oxide is formed by high-k and low-k dielectric material on the source and drain side respectively. The asymmetrical gate oxide decreases the tunneling width at the drain-channel (JDC) and source-channel (JSC) junctions and improves ON-current (ION). The buried oxide above the degenerated P+ substrate determines the tunneling width at the JDC and minimizes the ambipolar current. The device simulations show a low OFF-current (IOFF) of 4.21× 10−17 A/μm, a greater ION of 4.12× 10−4 A/μm, average and point subthreshold swing (SS) of 29.12 mV/dec and 19.38 mV/dec respectively for HfO2− SiO2 gate oxide. The above-mentioned result enables the device to be opted for low power applications. [ABSTRACT FROM AUTHOR]

A novel high-k dielectric material is proposed for InGaN/GaN–LED to improve the performance. The proposed LED is analyzed and benchmarked with conventional LED using Technological Computer Aided Design (TCAD). The qualitative consistency of the optical characteristics of LED in this work has been observed that validate the TCAD simulation. Further, it is observed that proposed LED recorded higher luminous power and internal quantum efficiency (IQE) than that of conventional LED. At the injection current of 600 mA, the proposed and conventional LED yielded luminous power of 1600 mW and 1400 mW, respectively. Further, IQE of the proposed LED is higher than that of conventional LED by 12%. The improvement in the optical performance is attribute to high-k dielectric material induced additional electric field and radiative recombination rate. Thus, the proposed LED with high-k dielectric material is an outstanding device in lightning application. [ABSTRACT FROM AUTHOR]

A novel edge-termination concept using extreme permittivity dielectrics is proposed to effectively manage electric fields in vertical power-devices. This method is expected to be particularly significant for wide band-gap semiconductors, where field termination is a significant challenge due to material and process limitations. Detailed two-dimensional device simulation is used to prove the efficacy of this idea, and to demonstrate that peak electric fields are significantly reduced by this method. We also show an analytical model that gives an intuitive picture into the mechanism of high-permittivity dielectric field plate. Low process complexity and flexibility in the design of power devices can be achieved. We show that junction termination efficiency can be increased from 22.7% (no junction termination) and 50% (conventional field plate) to 73% (high-permittivity-terminated device). [ABSTRACT FROM AUTHOR]

An improved subthreshold analytical model of Germanium source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET Ge(SRC)-DH-DD-TM-SG-TFET is proposed. The dielectric gate oxide structure is comprised of Silicon-dioxide and Hafnium oxide. The high-K dielectric materials overcomes the Short Channel Effects caused by ultrathin silicon devices. The subthreshold analysis is carried out by solving a 2-D Poisson's equation using the parabolic approximation method. The electrical characteristics of Ge(SRC)-DH-DD-TM-SG-Tunnel FET are analyzed using a 3-D Sentaurus TCAD device simulator and compared with the silicon based single halo and triple material surrounding gate TFET structures. The proposed model shows a lower ambipolar current and a better ION/IOFF ratio of 106. Moreover, the influence of germanium/silicon in dual dielectric materials has reduced the tunneling barrier width and the ON current (10−4 A/μm) of the proposed device and improved at the level of CMOS transistors. [ABSTRACT FROM AUTHOR]

The present study reveals the novel structure of nanoscale silicon-on-insulator fin field effect transistor (FinFET) in which an extra insulator layer (EIL) is injected into the silicon active layer. The key idea in this work is to control the hot electron effect by reducing the critical electric field near the drain region. The high- k dielectric $$\hbox {HfO}_{2}$$ is located between the silicon active layer and drain region under the gate oxides, where the average lateral electric field in the post-saturation region is high due to the function of the gate. The results of simulations reveal improvement in the hot electron reliability of EIL-FinFET in comparison to conventional FinFET (C-FinFET). In the proposed structure, the insulator region $$\hbox {HfO}_{2}$$ decreases the electric field in the channel and drain regions, especially near the Fin corners. Therefore, reducing the hot carrier effect (HCE), brings about more efficiency in the operation of the proposed structure in comparison with that of C-FinFET. Furthermore, the performance improvement of the proposed structure has been investigated using three-dimensional and two-carrier device simulator. In addition to that, the HCE, off current, and gate current in both the devices are compared to demonstrate the high reliability of the EIL-FinFET in complementary metal oxide semiconductor devices. [ABSTRACT FROM AUTHOR]

In the present study, Zr xLa 1−xO y amorphous nanostructures were prepared by the sol–gel method such that the Zr atomic fraction ( x) ranged from 0% to 70%. An analytical model is described for the dielectric constant ( k) of Zr xLa 1−xO y nanostructures in a metal–oxide–semiconductor (MOS) device. The structure and morphology of Zr xLa 1−xO y film was studied using x-ray diffraction, scanning electron microscopy, atomic force microscopy, and transmission electron microscopy. Elemental qualitative analysis was performed using energy-dispersive x-ray spectra and a map that confirmed the findings. Preliminary information on the influence of thermal annealing on the morphological control of Zr xLa 1−xO y amorphous nanostructures is presented. The dielectric constant of the crystalline Zr 0.5La 0.5O y thin film is about 36. Electrical property characterization was performed using a metal–dielectric–semiconductor structure via capacitance–voltage and current density–voltage measurements. [ABSTRACT FROM AUTHOR]

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I/ I ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high- k dielectric and low- k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I/ I (∼10). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance. [ABSTRACT FROM AUTHOR]

In this paper, a new high-voltage AlGaN/GaN HEMT (High Electron Mobility Transistors) with Field-Plate and high-k dielectric stack, Graded two-dimensional electron gas (2DEG) Channel Field-Plate Stack dielectric (GCFPS) HEMTs structure has been reported. The proposed structure has shown enhancements of the performances of the GaN-based HEMTs taking into account the effects of spontaneous and piezoelectric polarization fields. In order to analyze this structure, a 2D analytical model has been developed where the expressions for 2D channel potential and electric field distribution have been derived. It was shown that the GCFPS design exhibits significantly reduction of the electric field peaks along the 2DEG channel. Therefore, the breakdown voltage (BV) is greatly improved in comparison with the standard AlGaN/GaN FP-HEMTs. The developed model is validated by the good agreement with the 2D simulated data. [ABSTRACT FROM AUTHOR]

The combination of full Ni silicidation (Ni-FUSI) gate electrodes and hafnium-based high- k gate dielectrics is one of the most promising replacements for poly-Si/SiO2/Si gate stacks for the future complementary metal–oxide–semiconductor (CMOS) sub-45-nm technology node. The key challenges to successfully adopting the Ni-FUSI/high- k dielectric/Si gate stack for advanced CMOS technology are mostly due to the interfacial properties. The origins of the electrical and physical characteristics of the Ni-FUSI/dielectric oxide interface and dielectric oxide/bulk interface were studied in detail. We found that Ni-FUSI undergoes a phase transformation during silicide formation, which depends more on annealing temperature than on the underlying gate dielectric material. The correlations of Ni–Si phase transformations with their electrical and physical changes were established by sheet resistance measurements, x-ray diffraction (XRD), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) analyses. The leakage current density–voltage ( J– V) and capacitance–voltage ( C– V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the postdeposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current and eliminate hysteresis in the C– V curves. In addition, the changes in chemical bonding features at HfO2/Si and HfSiO/Si interfaces due to PDA treatment were evaluated by XPS measurements. XPS analysis provides a better interpretation of the electrical outcomes. As a result, HfSiO films exhibited superior performance in terms of thermal stability and electrical characteristics. [ABSTRACT FROM AUTHOR]

This work presents vertical flash memory devices with protein-assembled PbSe nanocrystals as a floating gate and Al2O3 as a control oxide. The advantage of a vertical structure is that it improves cell density. Protein assembly improves uniformity of nanocrystals, which reduces threshold voltage variation among devices. The introduction of Al2O3 as a control oxide provided lower voltage/faster operation and hence less power consumption compared with the devices fabricated with SiO2. The integration of Al2O3 appeared to be compatible with the protein assembly approach. In conclusion, Al2O3 has the potential to become the high- k control oxide due to its relatively high electron/hole barrier heights, and high permittivity. [ABSTRACT FROM AUTHOR]

We demonstrate ultra-thin (<150 nm) Si1-xGex dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si1-xGex interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si1-xGex interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process. [ABSTRACT FROM AUTHOR]

The three dimensional (3D) electrostatics of carbon nanotube field-effect transistors (CNTFETs) is studied by solving the Poisson equation self consistently with equilibrium carrier statistics of CNTFETs. The 3D Poisson equation is solved using the method of moments. We examine how the 3D environment affects the electrostatics of a 30 nm intrinsic CNT under equilibrium conditions. We show that for a CNTFET with a planar gate, the scaling length (the distance by which the source and drain fields penetrate into the channel) is mostly determined by the gate oxide thickness. The contact geometry can also play an important role on the scaling length. A smaller contact results in shorter scaling length and better gate control. We finally show that the top gated geometry offers obvious advantage over the bottom gated geometry in terms of gate electrostatic control. [ABSTRACT FROM AUTHOR]

In this article, we report the structural and electrical properties of metal-ferroelectric-high k dielectric-silicon (MFeIS) gate stack for non-volatile memory applications. Thin film of sputtered SrBi2Nb2O9 (SBN) was used as ferroelectric material on 5-15 nm thick high-k dielectric (Al2O3) buffer layer deposited using plasma-enhanced atomic layer deposition (PEALD). The effect of annealing on structural and electrical properties of SBN and Al2O3 films was investigated in the temperature range of 350-1000∘C. X-ray diffraction results of the SBN and Al2O3 show multiple phase changes with an increase in the annealing temperature. Multiple angle ellipsometry data show the change in the refractive index (n) of SBN film from 2.0941 to 2.1804 for non-annealed to samples annealed at 600∘C. For Al2O3 film, n<1.7 in the case of PEALD and n>1.7 for sputtered film was observed. The leakage current density in MFeIS structure was observed to two orders of magnitude lower than metal/ferroelectric/silicon (MFeS) structures. Capacitance-voltage (C-V) characteristics for the voltage sweep of −10 to 10 V in dual mode show the maximum memory window of 1.977 V in MFeS structure, 2.88 V with sputtered Al2O3 and 2.957 V with PEALD Al2O3 in the MFeIS structures at the annealing temperature of 500∘C. [ABSTRACT FROM AUTHOR]