Investigation of Hetero Buried Oxide and Gate Dielectric PNPN Tunnel Field Effect Transistors.

This paper investigates a novel hetero dielectric buried oxide and gate dielectric based PNPN tunnel field effect transistor (HDB-HDG-PNPN-TFET) using 2-D simulation. The buried oxide (BOX) is formed by SiO₂ below the channel and source, HfO₂ beneath the drain region. The asymmetrical gate oxide is formed by high-k and low-k dielectric material on the source and drain side respectively. The asymmetrical gate oxide decreases the tunneling width at the drain-channel (J_DC) and source-channel (J_SC) junctions and improves ON-current (I_ON). The buried oxide above the degenerated P⁺ substrate determines the tunneling width at the J_DC and minimizes the ambipolar current. The device simulations show a low OFF-current (I_OFF) of 4.21× 10⁻¹⁷ A/μm, a greater I_ON of 4.12× 10⁻⁴ A/μm, average and point subthreshold swing (SS) of 29.12 mV/dec and 19.38 mV/dec respectively for HfO₂₋ SiO₂ gate oxide. The above-mentioned result enables the device to be opted for low power applications. [ABSTRACT FROM AUTHOR]