Design and Application of Silicon on Insulator Based SiGe VTFET in IIR Filter by Balanced Truncation (BT) Method of Model Order Reduction.

In this paper, N-type and P-Type low power SiGe Silicon on Insulator Vertical TFET (SOI-VTFETs) are designed and then their drain current is investigated. The designed structures are calibrated with the reported structures considering the same model's environment for the validation of the design. Here, several advantages of SOI have been incorporated so that the low-voltage with low power (LVLP) VLSI designs digital circuits can be easily realized. Gate staking of high k -dielectric (HfO₂) material with SiO₂ was used to prevent the loss of the Lattice misfit structure using the equivalent oxide thickness approach. The proposed device's highest ON current and largest ON/OFF current are claimed to be (3.62 × 10⁻⁴ A/m) and (10¹³), respectively. Then the designed device is used to implement the full adder and the Infinite Impulse Response (IIR) filters. It is found that the performance of IIR filters is much enhanced over Finite Impulse Response (FIR) filters to keep flat response for altogether trial rates. The total delay of the IIR decimation filter via Merged Delay Transformation (MDT) is 0.181 ns with a Power Delay Product (PDP) of 3.5767. The current method employs the Routh Hurwitz Array method's advantages to derive the reduced-order denominator polynomial, and the reduced order numerator is obtained based on the resultant denominator polynomial. This order reduction technique is incorporated to reduce the number of delay units of the IIR filter and modified architecture offering a PDP of 0.22563, with its flat response initiated by SOI VTFET. The current model is productive in lowering area, power consumption, and stability over a specific sample rate or frequency. [ABSTRACT FROM AUTHOR]