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The GaN-on-Si technology for the upcoming RF/6G/mm-Wave applications requires a robust buffer design for enhanced device performance and improved reliability. The defect states present in the various layers of the buffer stack can have a detrimental impact on both the DC and the AC performance of the device, as they can interact with the 2DEG channel carriers and/or contribute to buffer leakage mechanisms. An important reliability concern is the dynamic-R ON , arising from the interaction of the 2DEG channel with the defects in the buffer stack and/or the defects in the barrier layer or barrier/cap interface. In this work, an improved and more robust current transient spectroscopy technique is used to extract the time constant spectra and the activation energies of various buffer defects. A thinner GaN channel layer is shown to increase the dynamic-R ON , while a specific buffer stack configuration is shown to have a considerable impact the dynamic-R ON .

We introduce a set of new characterization techniques for the direct defect analysis of the sidewall surfaces of Nano-ridge, Nanowire, and FinFET based devices, being used in current (and future) logic and RF technologies. We demonstrate the application of these techniques on GaAs mesa, Nano-ridge, and InGaAs nano-wire based PIN diodes where surface defect densities are difficult to extract currently. We show that a close match in extracted density, with both measured data and calibrated TCAD simulations of above device types, is achieved validating the applicability of the techniques.

The analysis and mitigation of substrate-related RF losses and non-linearities is crucial to enable GaN HEMTs on silicon for front-end transceivers for 5G and beyond. Here, for the first time, the impact of material growth and HEMT fabrication process on the substrate RF losses and linearity is studied using the effective substrate resistivity, ρ eff , and 2nd harmonic power, H2, figures-of-merit. It is shown that CPWs on fully-processed, GaN-on-high resistivity (3-6 kΩ•cm), 200 mm CZ-Si wafers can achieve H2 levels ~ -85 dBm (at P out ~15 dBm) with ρ eff ~1 kΩ•cm.

This paper describes the application of Deep Level Transient Spectroscopy and Generation-Recombination Noise Spectroscopy to the study of trap levels in III-V and III-N materials and devices.

A high gate-stack breakdown voltage is desired to enable the GaN-on-Si (MIS)HEMT device technology for upcoming RF/5G and mm-Wave applications. In this work, we show that the gate field-plate length (LGFP) has a considerable impact on the gate-stack TDDB lifetime for different gate-stack processing conditions and varying AlGaN barrier thickness. The TDDB lifetime is observed to increase with LGFP for devices suffering from high pre-stress gate-leakage, while it is observed to reduce with LGFP for devices with low gate-leakage and high RON dispersion. In devices with thinner AlGaN barrier, the higher RON dispersion results in further reduction of the TDDB lifetime. Additionally, the impact of L GFP on the TDDB lifetime is observed to reduce with thinner AlGaN barrier under similar processing conditions These results indicate a strong correlation between the gate-leakage and the barrier/cap interface properties, and their combined effect on the TDDB lifetime.

In this paper MISHEMTs with two different gate dielectrics (Al 2 O 3 and SiNx) are analyzed focusing on some analog figures of merit like transconductance, output conductance, transistor efficiency, Early voltage and intrinsic voltage gain. The Al 2 O 3 dielectric MISHEMT presented a degraded output characteristic in the bias range studied with a large self-heating turning the analog parameters impossible to be determined. The gate leakage of the SiNx MISHEMT is very high which degrades the subthreshold regime, decreasing the transistor efficiency at weak inversion, but the DIBL is much better than for the Al 2 O 3 devices. The SiNx devices present much better output characteristics resulting in a relatively large Early voltage and intrinsic voltage gain in strong inversion for this kind of devices up to 84 V/V (38.5 dB). The degradation with the temperature is small (around 1.5 dB from 25 °C to 150 °C) at strong inversion operation regime.

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow $( . Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar $\mathrm{I}_{\mathrm{on}}-\mathrm{I}_{\mathrm{off}}$ device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.

GaN-channel based transistors are ideally suited for RF/5G applications and also provide the promise of monolithic integration on a conventional Si-platform. Due to the wide scope of high electron mobility GaN transistor architectures, their reliability assessment is essential to ensure their successful deployment in low-power applications such as mobile computing devices, as well as high-power applications such as autonomous vehicles and base stations. We identify the most important DCreliability metrics necessary for fair benchmarking of future GaNon-Si RF transistors. A detailed analysis of the shortlisted DCreliability parameters for three device types, namely MOSFETs, MOSHEMTs/MISHEMTs and HEMTs is presented. MOSHEMT/MISHEMT is identified as the most robust device architecture, due to the presence of a barrier layer alleviating the impact of certain degradation mechanisms. Defect distributions in the gate-stack of MOS devices are extracted using defect band modelling technique. MOSHEMT devices are shown to undergo negative and positive Bias Temperature Instability (BTI) under specific ranges of positive gate-overdrive, thereby demonstrating the importance of correctly estimating the oxide field for MOSHEMT devices. Degradation map methodology is partially developed to distinguish the different gate-oxide degradation mechanisms and model the device lifetime pertaining to each of the mechanisms.

Photodetectors and photovoltaic devices composed of direct bandgap semiconductor materials absorb visible to infrared wavelengths within a few micrometers of material. Minority carrier diffusion lengths in such materials are critical in designing these optoelectronic devices for particular applications. Minority holes in InGaAs on InP are reported between 0-100°C for doping concentrations ranging between non-intentionally doped (NID) to 5E16 cm⁻³. At room temperature, values range between 81±8 μm for the NID sample to 34±1 μm for 5E16 cm⁻³. These values appear constant over the temperature range explored, implying that lifetime and mobility balance out., 2019 IEEE SENSORS, October 27-30, 2019, Montreal, QC, Canada

We report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools, and discuss the performance tradeoffs, limitations and solutions. The main highlights of process optimization include low RF transmission loss (0.15 dB/mm at 20 GHz), state-of-the-art contact resistance (R C ) of 0.14 Ω mm for a non-Au, low thermal budget ( BD ) of >300 V (pre and post device processing). We show that MISHEMTs, which feature the highest field effect mobility (μ FE ), >2000 cm2/V.s, and the best 1/f noise performance, have the potential to outperform the other device types in terms of device scalability for high frequency operation.

In this paper, we demonstrate GaAs/InGaP HBTs grown on a 300 mm Si substrate. A DC current gain of ~112 and breakdown voltage, BV CBO , of 10 V is achieved. The emitter-base and base-collector diodes show an ideality factor of ~1.2 and ~1.4, respectively. This demonstration shows the potential for enabling a hybrid III-V CMOS/ technology for 5G and mm-wave applications, not limited to GaAs but which can also be extended to InGaAs on a 300 mm Si substrate.

A High Pressure Time Projection Chamber (HPTPC) with hybrid optical and charge readout has been developed and tested for use in future neutrino oscillation experiments. In this talk we present preliminary results demonstrating the optical and charge readout.

Numerical device model calibration of InGaAs/InP double-heterostructure p-I-n junctions is performed at room temperature using guarded test structures of various areas and investigating the contributions from minority carrier diffusion, depletion region generation and finally perimeter (shunt) leakage. The perimeter leakage is determined to be 0.5 pA/cm, whereas the depletion region contributes 2.2 nA/cm²; the bulk diffusion contribution is excluded via the guard ring but can be computed analytically to be 2.0 nA/cm². Reproducing the experimental test structures within the numerical modeling environment accurately reproduces the data based on calibrating the diffusion length and SRH lifetime., 2019 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD), July 8-12, 2019, Ottawa, ON, Canada

We proposed a simple noise model based on the photon transfer method for the testing of a hybrid optical sensor for imaging in short-wavelength infrared regime. The proposed testing procedure allowed us to separate the noise sources and then work on noise mitigation., 2019 IEEE Research and Applications of Photonics in Defense Conference, RAPID 2019, August 19-21, 2019, Miramar Beach, FL, USA

This paper describes the design of a 28 GHz power amplifier (PA) in a commercial GaAs mHEMT technology using concepts that are typical for mm-wave CMOS design. Simulations show a 1dB output compression point of around 23 dBm with a 30% power-added efficiency (PAE) at 28 GHz, while providing a gain of 12 dB. Comparison with the performance of a similar 28 GHz fully-depleted Silicon-On-Insulator (FDSOI) PA shows an increase of the compression point with 10 dB while efficiency is comparable. The high compression point of this GaAsPA offers a margin for system optimization such as a reduction of the number of antennas for beamforming.

Electron traps are detected from vertical n+-GaAs/n−-InGaP/p+-GaAs diodes with deep-level transient spectroscopy (DLTS). Combining lock-in window (t w ) varying DLTS and double-correlation DLTS (DDTLS), we assign the electron traps to surface states at the sidewalls of the diodes. The methodology is introduced in the paper.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of “reliability” anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

In this work, we will address the opportunities and technology challenges related to next generation mobile communication. To enable the required data rates and reliability for 5G applications, Si CMOS will need to be complemented with new materials and device architectures like III-V or GaN devices to enable at the same time the targeted speed and power efficiency of these systems. Heterogeneous integration, either monolithic or using 3D integration, will be a key enabler to achieve this.

FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, I on =500μA/μm at I off =100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si 0.3 Ge 0.7 SRB.

As protection intelligent electronic devices (IEDs) have evolved, their communications and reporting capabilities have become more advanced. Protective relays can store, with high-accuracy time stamps, not only records of protection elements pertinent to the operation of the relay itself but also the arrival and departure of high-speed incoming and outgoing data that are used to coordinate other devices' protection algorithms. All the data can be sifted through and analyzed to locate maintenance indicators and to correct undesirable behaviors before a larger problem is created within the system. Some communications testing requirements are already outlined in NERC PRC-005-02 — Protection System Maintenance. This paper investigates how, by using the communications and reporting capabilities of these modern IEDs, a continuously running monitoring system can quickly identify and report signal transmission timing or delivery degradation in a protection system using high-speed peer-to-peer signals. This monitoring system functions regardless of protection scheme protocol selection or network design variations, and it provides immediately actionable data by delivering reports that indicate the exact contact or internal bit in a specific relay or set of relays involved in the problem.

An overview is given on how to tackle the question of the electrical activity of extended defects which are inevitably present in hetero-epitaxial III-V layers on silicon. Analysis methods are described which rely on simple device structures containing a specific type of extended defect (here, threading dislocations). Applying the same methods to real scaled FinFETs is rather challenging. Instead Generation-Recombination noise spectroscopy provides data that can be compared with other more standard techniques, like Deep-Level Transient Spectroscopy (DLTS) in order to identify the presence of an electrically active extended defect in the channel material.

We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

New precise synchronization strategies of distributed intelligent electronic devices (IEDs) and high-speed data acquisition and exchange of measured and calculated signals are being used to solve ever increasingly complex power system problems. Many specific problems addressed in this paper previously went unaddressed because processing and communications were not proven fast enough nor precise enough for wide-area logic schemes. IEEE C37.118 synchrophasor protocol is a very useful communications method for observation and reaction to distributed synchronized measurements and calculations. However, this paper illustrates using internationally standardized IEC 61850 GOOSE messages for better performance. These messages are implemented by many different IED manufacturers and have attributes that make them faster and easier to deploy over wide-area networks. This paper illustrates simple and effective mechanisms to use time-domain automation to build, test, and monitor elegant local- and wide-area logic and control applications. Field-proven benefits of design and implementation of installed systems demonstrate the utility of these methods and enable others to recognize new important benefits and applications.