29 results on '"Vandeweyer, T."'
Search Results
2. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application
3. A new complementary hetero-junction vertical Tunnel-FET integration scheme
4. Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry
5. Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application
6. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation
7. Investigation of Forming and Its Controllability in Novel HfO2-Based 1T1R 40nm-Crossbar RRAM Cells
8. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
9. Record low contact resistivity to n-type Ge for CMOS and memory applications
10. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout
11. Immersion lithography and double patterning in advanced microelectronics
12. A 400GHz fMAX fully self-aligned SiGe:C HBT architecture
13. Redevelopment of the Schoonebeek Oil Field, Netherlands – Tackling a Giant with the Necessary Detail
14. Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
15. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length
16. A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process
17. Gatestacks for scalable high-performance FinFETs
18. A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
19. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography
20. Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency
21. Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology.
22. Comprehensive approach to MuGFET metrology.
23. Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques.
24. Air gap integration for the 45nm node and beyond.
25. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application.
26. Air gap integration for the 45nm node and beyond
27. A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
28. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout.
29. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.