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This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processor’s multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature. [ABSTRACT FROM AUTHOR]

This article presents a “three unary bits +five splitting bits + four binary bits” segmented 500-MS/s current-steering digital-to-analog converter (DAC). The proposed splitting decoding method is between the unary decoding and binary decoding, in terms of number of switched elements. It can optimize the differential nonlinearity and output glitches of DAC, with a more simplified circuit scale than unary decoding method. Due to the data-transmission topology, both the proposed thermometer and splitting decoders feature lower transistor count and occupy less area than other competitors. Their low latency accommodates to fast synchronization control of current source switches and its beneficial to the spurious-free dynamic range (SFDR) improvement of DAC. When implemented in a 0.18- $\mu \text{m}$ CMOS process, the 12-bit DAC occupies an active area of 536 $\mu \text{m}\,\,\times \,\,340\,\,\mu \text{m}$ , with the proposed decoders occupying only 28 $\mu \text{m}\,\,\times \,\,75\,\,\mu \text{m}$. The DAC dissipates 17.20 mW at 500 MS/s with a 1.8-V analog supply and a 1.2-V digital supply. The differential and integral nonlinearities are measured to be 0.28 and 1.16 LSB, respectively. The DAC also features SFDRs of 68.83 and 62.06 dB for input signals of 6.34 and 239.74 MHz, respectively. [ABSTRACT FROM AUTHOR]

Functional test sequences are used as manufacturing tests to complement scan-based tests. Functional test sequences target defects in the functional logic of the circuit. However, they may fail because of defects in the scan logic that prevent the circuit from operating correctly in functional mode. It is advantageous to detect such defects by dedicated test sequences before attempting to apply functional test sequences. The computation of dedicated test sequences for faults in the scan logic is the topic of this brief. The procedure described in this brief accepts a pool of functional test sequences. It identifies subsequences from the pool that are effective for detecting faults in the scan logic while balancing their lengths. It then compacts the sequences to reduce their total length further. Experimental results for benchmark circuits demonstrate large variations among different circuits in the total length of the sequences and significant reductions in the total length for all the circuits considered. [ABSTRACT FROM AUTHOR]

It is known that rapid single-flux-quantum (RSFQ) circuit technology and its energy-efficient derivatives are considered promising technology in superconducting digital applications. Given an $n$ -stage logical netlist with a set of logic gates and D-type flip-flops (DFFs) in an RSFQ circuit, based on the construction of three different gate components inside one gate column, the RSFQ circuit can be treated as a pipelined architecture with $m$ gate components inside $n$ gate columns. To minimize the routing area in the pipelined architecture of an RSFQ circuit, an efficient algorithm can be proposed to minimize the total vertical wirelength in a fixed-order placement. First, based on the construction of the initial fixed-order placement and the reduction of the total vertical minimum length using one upward-shifting operation, a propagation-based fixed-order placement (PFP) can be obtained by using an on-column placement process. Based on the determination of the available gate clusters inside the gate columns, an iterative matching-based shifting process can be further used to reduce the total vertical wirelength in a fixed-order placement. Finally, based on the determination of the available gate blocks in a modified fixed-order placement, an iterative shifting process can be used to reduce the total vertical wirelength in the modified fixed-order placement. Compared with the modified simulated-annealing (SA)-based algorithm with three initial temperatures, 100, 1000, and 100000, the experimental results show that our proposed algorithm can use 3.4%, 2.7%, and 2.1% of CPU time to reduce 3.5%, 0.5%, and 0.3% of the total vertical wirelength in a final fixed-order placement for five tested RSFQ circuits on the average, respectively. Clearly, the proposed algorithm is efficient in the construction of a fixed-order placement in an RSFQ circuit. [ABSTRACT FROM AUTHOR]

The functionality of polymorphic circuits can be altered using a control variable. Owing to the multifunctional embodiment in polymorphic circuits, they are helpful to reconfigure circuit behavior from the gate level to the system level, either on the fly or off-line. The polymorphic circuit approaches available in the literature are either based on custom nonlinear circuit designs or special emerging devices, such as ambipolar FET and configurable magnetic devices. While some of these approaches are inefficient in performance, the other approaches involve exotic devices. We have proposed a novel polymorphic circuit design approach based on crosstalk (CT) computing, where we leverage deterministic signal interference between nanometal lines for logic computation and reconfiguration. In this article, we elaborate upon the polymorphic circuit design in CT computing through mathematical formulation, which conveys the rationale to generalize and achieve a wide variety of polymorphic circuits, and then demonstrate a comprehensive list of polymorphic circuit designs. In addition, all circuits are characterized and benchmarked against CMOS circuit implementations to gauge the benefits. Finally, we compare the CT polymorphic circuit approach with other approaches in the literature and highlight its unique features and limitations. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to CT computing, which leads to benefits in the circuit power, performance, and area (PPA). Our circuit designs, simulation, and PPA characterization results show that the polymorphic CT circuits provide $3\times $ improvement in transistor count, $2\times $ improvement in switching energy, and $1.5\times $ improvement in speed for polymorphic logic circuits. In the best-case, the transistor count reduction is $5\times $. [ABSTRACT FROM AUTHOR]

A novel wideband analog phase shifter employing a self-tuning $I/Q$ generator is proposed in this article. It can provide 360° continuous phase shift with very low rms gain and phase error while consuming 22.8 mW from a 1-V supply with the phase shifter core dissipating only 11.2 mW. Cartesian-combining method has been employed to provide better control over sidelobes in a phased array network application. The phase shifter is fabricated in 65-nm CMOS and occupies a core area of only 0.12 mm2. Employing the self-tuning $I/Q$ generator in an error feedback control loop, a single-stage poly-phase-filter (RC -PPF) is tuned by changing the gate voltage of triode-regime nMOS resistors. This self-tuning-loop provides $I/Q$ amplitude imbalance and phase error under 0.3 dB and 1.1°, respectively. This reduces the rms gain error and phase error of the phase shifter below 0.4 dB and 1.6° respectively for a 5-GHz bandwidth (25–30 GHz). The I/Q generator circuit consumes a dc-bias current of only 2 mA. The tunable insertionloss varies by around 7 dB and the 1-dB compression point IP1dB is in the range $-7.5\,\,\pm \,\,2.6$ dBm near the center frequency. The proposed phase shifter can be a good fit for radio detection and ranging (RADAR) within the $K$ - and Ka -bands, as well as, for future 5G application in the 26.5–29.5 GHz range. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is a type of logic computation based on stochastic bit stream instead of the binary numbers (BNs). It is pseudo-analog computation in the digital domain that can realize multiplication, addition, and complex function computations. In this brief, a new encoding method, referred to as amplitude and frequency encoding (AFE) for SC, is presented. It extends SC to use multibit streams instead of bit streams to represent data. This method still uses the expectation of streams to achieve computation. Compared with the conventional stochastic bit stream, AFE realizes low-latency and low-area occupation than the conventional SC method. The rationality of the circuits is also examined from a mathematical perspective. The hardware logic circuit of AFE SC, including the multiplier, adder, and converter, was designed and implemented by a field-programmable gate array (FPGA). In addition, the latency of the computing, area, and precision of AFE SC was measured based on the FPGA board. [ABSTRACT FROM AUTHOR]

In this article, an efficient architecture for a low-power, high-resolution flash analog-to-digital converter (flash ADC) is presented. It operates at 12-bit resolution with a sampling frequency of 1.1 GS/s. The architecture is a segmented one consisting of three subflash ADCs that we call SADC1, SADC2, and SADC3. During the operation, SADC1 detects the MSB bit, and SADC2 detects the intermediate bits, while SADC3 detects the finer bits of the flash ADC. Furthermore, SADC1 has a 1-bit resolution, SADC2 has a 6-bit resolution, and SADC3 has a 5-bit resolution. The binary operation related to 12-bit resolution is achieved by combining the subflash ADCs, thermometer digital outputs, and an encoder. The ADC has been fabricated in Global Foundry (GF) 65-nm standard CMOS process. The measured performance parameters show a differential nonlinearity (DNL) of ±0.24 LSB, an integral nonlinearity (INL) of ±0.45 LSB, a signal-to-noise and distortion ratio (SNDR) of 64.55 dB, a spurious-free dynamic range (SFDR) of 73.9 dB, and an effective number of bits (ENOB) of 10.43 bits. Also, power consumption is found to be 15.10 mW at 1.1-GS/s sampling frequency and 1.2-V supply voltage. The ADC achieves an FOM of 9.95 fJ/conversion-step (c-s) at the Nyquist input frequency and occupies a core area of 0.084 mm2. [ABSTRACT FROM AUTHOR]

Accurate characterization of radiation-induced soft errors is a critical step toward understanding the impact of these glitches on circuit and system reliability. With process scaling, there has been exponential increase in number of transistors that can be packed on a die which, in turn, results in higher sensitive node count and persistent soft error susceptibilities. In this work, a novel circuit technique employing higher sensitivity toward soft errors is proposed. The circuit makes use of current-starved gates with bias knobs to fine-tune both measurement resolution and strike sensitivity enabling accelerated and efficient induction of errors in a limited-time irradiation test environment. The back-sampling chain (BSC) circuit can measure individual radiation-induced transient pulse with as low amplitude as $0.3\times $ VDD while maintaining a high measurement resolution for pulsewidth characterization. The bias knobs allowing tuning of sensitivity and resolution enable, for the first time, a strike pulse waveform reconstruction methodology that can be used to calibrate current pulse models for assessing soft error rate (SER) sensitivity of standard logic gates. [ABSTRACT FROM AUTHOR]

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier’s specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18-μm CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation. [ABSTRACT FROM AUTHOR]

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell. [ABSTRACT FROM AUTHOR]

This article focuses on thwarting reverse-engineering attacks and intellectual property (IP) theft by leveraging charge-recycling adiabatic circuits. The adiabatic circuit operation has recently received attention for the Internet-of-Things (IoT) applications due to high energy efficiency and enhanced security characteristics. Such applications typically consist of resource-constrained designs and are often deployed in the field, making them particularly vulnerable to malicious attacks. PhaseCamouflage is a circuit obfuscation technique that leverages the inherent phase differences (PDs) in power supply voltage of adiabatic logic gates and exhibits strong resistance against structural/removal attacks. The proposed method relies on inserting camouflaged PDs in the power supply voltage of subsequent logic gates while still producing a functional netlist. PhaseCamouflage is a unique logic obfuscation technique with low overhead, particularly applicable to pervasive computing applications where both efficiency and security are of primary concern. [ABSTRACT FROM AUTHOR]

As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for accurate gate modeling. Industrial gate models, however, are precharacterized assuming capacitive loads, which poses significant challenges to the approximation of the highly resistive load interconnect with an effective capacitance (Ceff). In fact, most related works are either computationally expensive or unable to approximate the output slew. Furthermore, they require additional precharacterization and ignore the Miller effect. In this article, we present an iterative methodology for fast and accurate gate delay estimation. The proposed approach accurately computes the driver output waveform, using closed-form formulas to calculate a Ceff per waveform segment, while accounting for their interdependence. Thus, it allows for variable analysis resolution exploiting an accuracy/runtime tradeoff. In contrast to prior works, our approach is compatible with conventional CSMs and considers the impact of Miller capacitance. We evaluate our method on representative driver-load test circuits consisting of interconnects with arbitrary RC characteristics and ASU ASAP 7-nm standard cells. The proposed method achieves 1.3% and 2.5% delay and slew root-mean-square percentage error (RMSPE) against SPICE, respectively. In addition, it provides high efficiency, as it converges in 2.3 iterations on average. [ABSTRACT FROM AUTHOR]

First-in–first-out (FIFO) line buffers occupy considerable logic gates and consume significant power of the feature from accelerated segment test (FAST) image corner detection engine. In this study, a FAST-Chip (FAST-C) engine is proposed to eliminate these drawbacks. It comprises three core techniques: arch pixel estimation (APE), hardware-efficient line buffer (HLB), and interleaving-based parallel access (IPA). APE can save three line buffers using gradient information for pixel prediction. With APE, the number of line buffers can be saved by 33%. HLB effectively organizes static random access memories (SRAMs) as line buffers to store reference pixels rather than FIFO. It demands less power and fewer logic gates. IPA makes the FAST-C engine have regular data paths and smooth data scheduling, keeping hardware throughput. Experiment results show that the accuracy difference between FAST and FAST-C is as minor as 2.29%. The proposed FAST-C engine is implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS process with a logic gate count of 223k, where the line buffers are included. Its frequency is 613 MHz with a power consumption of 1.18 W. Its maximum throughput can sufficiently support 3840 × 2.160 (4k) @ 60 frames per second (fps). Compared with sophisticated FAST engines, the FAST-C engine presents outstanding energy efficiency (EE) and area efficiency (AE). [ABSTRACT FROM AUTHOR]

It is generally known that a considerable portion of flip-flops in circuits is occupied by the ones with mux-feedback loop (called self-loop), which is the critical (inherently unavoidable) bottleneck in minimizing total (always-on) storage size for the allocation of nonuniform multibits for retaining flip-flop states in power gated circuits. This is because it is necessary to replace every self-loop flip-flop with a distinct retention flip-flop with at least one-bit storage for retaining its state since there is no clue where the flip-flop state, when waking up, comes from, i.e., from the mux-feedback loop or from the driving flip-flops other than itself. This work breaks this bottleneck by safely treating a large portion of the self-loop flip-flops as if they were the same as the flip-flops with no self-loop. Specifically, we design a novel mechanism of steady-state monitoring, operating for a few cycles just before sleeping, on a partial set of self-loop flip-flops, by which the expensive state retention storage is never be needed for the monitored flip-flops, contributing to a significant saving on the total size of the always-on state retention storage for power gating. Through experiments with benchmark circuits, it is shown that our proposed method is able to reduce the total number of retention bits by 27.12% on average when at most 2-bit retention flip-flop is used, saving standby power by 19.41% compared with the state-of-the-art conventional method. [ABSTRACT FROM AUTHOR]

In this article, we present a novel logic design style, namely, memristor overwrite logic (MOL), associated with an original MOL-based computational memory. MOL relies on a fully digital representation of memristor and can operate with different memristive device technologies. Its integration in memristive crossbar arrays and computational memories allows the execution of bit and vector-level primitive logic operations in two computational steps at most. Promising features and performances are demonstrated through the implementation of $N$ -bit full addition using the proposed MOL-based computational memory. [ABSTRACT FROM AUTHOR]

This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general. [ABSTRACT FROM AUTHOR]

This brief presents an all-digital CMOS pulse-shrinking time-to-digital converter (TDC) with temperature-measuring capability for higher circuit value and cost saving. A pulse generator is proposed to generate either a time-added pulse or a temperature-sensing pulse. A cyclic delay line (DL) composed of a temperature-sensing DL and a pulse-shrinking DL becomes area efficient and achieves sufficiently wide dynamic range. A time subtractor that eliminates the effect of the offset error enhances accuracy. The proposed TDC is fabricated with TSMC 0.35- $\mu \text{m}$ CMOS process and has a small area of approximately 0.019 mm2. The effective time resolution is approximately 45 ps, with an integral nonlinearity of −0.5 to 0.85 least significant bit (LSB). The achieved temperature resolution is nearly 0.1 °C/LSB, with an inaccuracy of −1.35 °C to 0.7 °C for a range of 0 °C–90 °C. Experimental results prove that we have proposed the first TDC that successfully measures time and temperature. [ABSTRACT FROM AUTHOR]

This article presents a majority-logic device, called sttMAJ, based on spin-transfer torque magnetic tunnel junctions (STT-MTJs). sttMAJ devices make it possible to build Boolean and non-Boolean circuits without any transistors. We leverage a physics-based model of sttMAJ device to the design of different highly scalable current-mode logic circuits and neuromorphic-computing/image-processing applications. The functionality of sttMAJ-based circuits is verified using the SPICE circuit simulator. The simulation results reveal that the gate device not only provides a simple and powerful structure (in terms of implementing digital functions and image-processing applications with a small number of devices) but also offers high performance due to its better electrical properties. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) in recent years has been defined as a digital computation approach that operates on streams of random bits that represent probability values. SC can perform complex tasks with much smaller hardware footprints compared with conventional binary methods, but previous methods on SC circuits operated on serial bit streams, which leads to high-latency implementations. This article presents a significant improvement over previous work; it provides a deterministic parallel bit shuffling network that can use a simple deterministic thermometer encoding of data, resulting in zero random fluctuation and high accuracy, yet keeping the output bit-stream length constant. We use core “stochastic” logic circuits that do not employ constant coefficients, making them significantly smaller than traditional stochastic logic that use a significant amount of resources to generate such coefficients. Our experiments show that compared with previous SC methods, our method has up to $3\times $ smaller mean absolute error, and better area $\times $ delay and power efficiency. Compared with conventional binary methods, our method is better in terms of area $\times $ delay at 8-bit resolution. It shows better power efficiency ($40\times $ , $18\times $ , and $8\times $ Gops/W at 8-, 10-, and 12-bit resolutions) compared with conventional binary. [ABSTRACT FROM AUTHOR]

In this article, we propose an efficient circuit reliability analysis infrastructure utilizing on-demand transistor-accurate fault injection based on workload-specific distributional properties. A novel two-phase approach is developed to achieve circuit-level accuracy, via careful transistor-level precharacterization, and gate-level efficiency, via fast runtime fault generation. A time-consuming circuit characterization is performed once, and the result of the precharacterization is used multiple times at runtime to inject faults. Also, novel fault probability estimation and fault injection methods are developed. Fault probabilities are computed based on workload-specific voltage/temperature distribution, and faults are injected efficiently by scaling the computed fault probabilities. We demonstrate the proposed methodology on an OpenSPARC core targeting an implementation on a 32-nm technology node. Analysis indicates that the injector computes the system failure rate with 0.1-ms simulation overhead per injection while having circuit-level accuracy. [ABSTRACT FROM AUTHOR]

The effects of supply-induced frequency variations on single-ended tuning $LC$ voltage-controlled oscillator (VCO) which degrade the jitter performance of the clock are investigated. The first-order impact on the supply sensitivity is that the varactor’s effective capacitance varies with the supply voltage, with other second-order impacts attributed to commonly used capacitive bank and cross-coupled pairs. A compensation technique based on complementary varactors to improve the supply sensitivity of single-ended tuning $LC$ VCO is proposed with no extra power dissipation, nor phase noise degradation within the relative frequency band of interest, along with the discussion on the operating principle of the compensation technique. Both the NMOS cross-coupled and complementary cross-coupled $LC$ VCOs have been designed, demonstrating robust supply-insensitive performance over process, voltage, and temperature (PVT) variations. Prototyped oscillators were fabricated in a 0.18- $\mu {\mathrm{ m}}$ CMOS process to verify both the theoretical analysis and the effectiveness of the proposed technique. Measurement results show that the compensated topologies exhibit more than 93% reduction in periodic jitter versus the noncompensated counterparts, with the figures of merit (FoMs) among the best compared with previous supply insensitive works. [ABSTRACT FROM AUTHOR]

Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of xor–xnor circuit. In this article, a high-speed, low-power 10-T xor–xnor circuit is proposed, which provides full swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. The proposed circuit reduces the power delay product (PDP) at least by 7.5% than that of the available xor–xnor modules. Four different designs of FAs are also proposed in this article utilizing the proposed xor–xnor circuit and available sum and carry modules. The proposed FAs provide 2%–28.13% improvement in terms of PDP than that of other architectures. To measure the driving capabilities, the proposed FAs are embedded in 2-, 4-, and 8-bit cascaded full adder (CFA) structures. Results show that two of the proposed FAs provide the best performance for a higher number of bits among all the FAs. [ABSTRACT FROM AUTHOR]

Carbon-nanotube FETs (CNFETs) are potential successors to CMOS transistors; these emerging devices have a low intrinsic delay due to near-ballistic transport in carbon nanotubes (CNTs). As CNFETs are evaluated for circuit/system design, it is important to analyze variations in CNT process parameters. In this article, we present a systematic approach to quantify the impact of these imperfections on the transistor- and gate-level performances of CNT-based circuits. Process variations are investigated to identify the critical device parameters that have maximum impact on the device on-current. We also present a model that predicts the realistic CNFET yield in the presence of process variations. Finally, the impact of manufacturing defects, such as pinholes in the gate dielectric and parasitic CNFETs formed due to imperfect etching, are modeled and evaluated using HSPICE. [ABSTRACT FROM AUTHOR]

This brief presents a cost-efficient all-digital CMOS digital-to-time converter (DTC) that innovatively applies binary-weighted pulse expansion. The DTC consists of a pulse generator (PG) for pulse generation ($t_{p}$), a binary-weighted pulse-expanding circuit (BWPEC) as a main circuit for digital-to-time conversion, and a time subtractor (TS) for $t_{p}$ removal. Compared with the original pulse-expanding unit (PEU), a novel PEU with reduced complexity and a linear pulse expansion was developed for binary-weighted operation. The use of the BWPEC with the binary-weighted PEUs exhibits lower circuit complexity and considerably reduces the circuit cost compared to the original unary-weighted pulse-expanding circuit (PEC). A prototype of the 4-bit all-digital DTC was fabricated using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.35- $\mu \text{m}$ CMOS process. The fabricated DTC exhibited an area of 0.02 mm2 achieving twofold improvement considerably. The measured resolution was approximately 5 ps, with the integral nonlinearity being −1.2–1 least significant bit (LSB). Without requiring an advanced CMOS process, the pulse variation technique with a simple structure can easily achieve fine resolution. The DTC features cost-efficient pulse expansion with binary weights and low circuit complexity. [ABSTRACT FROM AUTHOR]

On-chip digital low-dropout (LDO) regulators enable fast dynamic voltage scaling, reducing power consumption. Integrating these regulators into a highly resistive environment has complicated the design of power delivery systems. With the increasing sensitivity of complex integrated systems to power noise, effective approaches to distribute on-chip LDOs are needed due to the limited metal resources. In this article, a methodology is proposed to distribute the pass gates of a system of on-chip digital LDOs. The distribution of the pass gates considers the location of the load currents to reduce voltage variations across the power grid. The proposed pass gate distribution topology reduces the maximum voltage variations across the grid, on average, by two to three times under nonuniform load distributions. [ABSTRACT FROM AUTHOR]

A 10-Gb/s on-chip 1-D eye-opening monitor (EOM) for receiver front-end equalizer boost gain adaptations is presented. The proposed EOM circuits report in real-time horizontal eye-openings using equalizer output by calculating the probability density of the waveform in the central row of pixels of the eye diagram. In addition, a novel multi-phase generator circuit with a delay gain calibration is also demonstrated. It is suitable for EOM circuits to generate a multi-phase sampling clock. The proposed 1-D-EOM circuit is included in a 10-Gb/s receiver design to verify its adaptation functions, and the circuit is implemented using the 65-nm CMOS technology. The sampling phase resolution is 1.5625 ps (where the time for one bit is 100 ps, with a total of 64 phases), and the response time is $64~\mu \text{s}$. The total power consumption of the EOM circuit is 1.5 mW with a 1-V supply voltage, and the circuit occupies a layout area of 60 $\mu \text{m}\,\,\times $ 450 $\mu \text{m}$. The results show that the reported horizontal eye-opening value is proportional to the value from a real eye diagram monitor from the test buffer. [ABSTRACT FROM AUTHOR]

Precharge half buffer (PCHB) is one of the major quasi-delay insensitive (QDI) asynchronous design paradigms, which has been utilized in several commercial applications due to its low power and inherent robustness. In industry, QDI circuits are often synthesized from a synchronous specification using custom synthesis tools. Design validation of the implemented QDI circuits mostly relies on extensive simulation, which may fail to detect corner-case bugs, especially in complex designs. Hence, a formal verification scheme for PCHB circuits is much needed. In this article, we present a formal verification methodology for PCHB circuits synthesized from a Boolean/synchronous specification, which is based on equivalence checking and can guarantee both safety (full functional correctness) and liveness (absence of deadlock). The approach is fast, scalable, and applicable to combinational as well as sequential PCHB circuits. We demonstrate the method using several multipliers, multiply and accumulate circuits (MACs), and IEEE International Symposium on Circuits and Systems (ISCAS) benchmarks. [ABSTRACT FROM AUTHOR]

Multiple emerging computing technologies based on, e.g., graphene, spintronics, resistive RAM, quantum computing, and others are being developed to enhance the capabilities of logic devices and circuits. The rapid growth in these technologies is synchronized with the decline of Moore’s law, thus promises to herald the era of Beyond CMOS technologies with a significant improvement in energy efficiency, reliability, performance, and manufacturability. These devices enable very different computing paradigms, e.g., neuromorphic computing, non-Boolean computing, and in-memory computing, thus making these platforms an interesting playground for circuit and application-developers alike. [ABSTRACT FROM AUTHOR]

Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the oxide, or misalignment during bonding, among others. Although considerable research effort has been made to improve the coverage of TSV testing, little attention has been paid to weak (resistive) open defects causing small delays. In this work, a postbond oscillation test strategy to detect such small delay defects is proposed. Variations in the duty cycle of transmitted signals after unbalanced logic gates are shown to help in the detection of weak open defects in TSVs. HSPICE simulations, including process parameter variations, have been considered, and results show the effectiveness of the method in the detection of weak open defects above 1 $\text{k}\Omega $. Experimental work on a 65-nm IC also corroborates the detection capability of the proposal. [ABSTRACT FROM AUTHOR]

The majority logic (ML) gate (MLG) is required in fast decoder implementations to protect memories from transient soft errors. In this paper, a novel MLG design is proposed; it consists of a pMOS pull-up network, an nMOS pull-down network, and an inverter. The proposed design is applicable to an arbitrary number of inputs $\gamma $ (and operating as a mirror circuit when $\gamma $ is odd). The proposed designs are simply requiring a small number of transistors; when simulated, they offer improved metrics such as reduction in delay, area, and power dissipation compared with existing designs found in the technical literature. When the combined power-delay-area product (PDAP) is considered, the advantages of the proposed designs are pronounced. The application of the proposed MLGs to design fast decoders for one-step ML decodable (OS-MLD) codes is also presented; the results show that the proposed MLGs are very efficient circuits for this coding application. [ABSTRACT FROM AUTHOR]

Conventional capless digital low-dropout (DLDO) regulators adopt either a high-speed clock or the burst mode at the expense of a larger quiescent current in order to overcome the degradation of the load transient response caused by the absence of an external capacitor, which causes high power consumption. In this paper, a capless DLDO regulator with a self-clocking burst logic for ultralow power applications is proposed. The self-generated clock in the burst mode of the proposed burst logic is activated temporally in order to achieve both faster load transient response and lower quiescent current. The proposed DLDO regulator is implemented in 14-nm FinFET CMOS technology. The quiescent current and figure-of-merit (FoM) of the proposed DLDO regulator are $0.69~\mu \text{A}$ and 0.097 ps, respectively, with an active area of 0.0035 mm2, excluding a 0.1-nF integrated output capacitor. [ABSTRACT FROM AUTHOR]

A fundamental operator in modern computational systems has a multitude of highly optimized implementations. In general-purpose systems, the width has grown to 128 bits, putting pressure on designers to use sophisticated carry lookahead or tree adders to maintain throughput while sacrificing area and energy. However, the typical workload mostly exercises the lower 10–15 bits. This leaves many devices on and unused during normal operation, reducing the overall performance. We hypothesize that bit- or digit-serial implementations for arbitrary-length streams represent an opportunity to decrease the overall energy usage while increasing the throughput/area efficiency of the system and verify this hypothesis by constructing an asynchronous digit-serial adder for comparison against its bit-parallel counterparts. [ABSTRACT FROM AUTHOR]

Transparent-scan is an approach to test compaction where scan shift cycles and functional capture cycles are interleaved in arbitrary ways as needed for detecting target faults. This is achieved by viewing the scan enable input as a regular primary input that can be assigned arbitrary sequences of zero and one values. This paper notes that transparent-scan leaves an unused combination of the scan enable and scan chain input values. This paper suggests that the unused combination can control design-for-testability logic to achieve better test compaction. At the cost of one additional EXCLUSIVE-OR gate for every state variable, and routing of the scan chain input to all the flip-flops, the extended transparent-scan approach described in this paper allows the values of the next-state variables to be complemented before they are latched in the flip-flops during a functional capture cycle. Extended transparent-scan is developed under bounded transparent-scan, where scan-in and scan-out operations of a conventional scan-based test set are maintained in order to limit the computational cost. Experimental results for transition faults in the functional logic of benchmark circuits demonstrate the additional test compaction that can be achieved with extended transparent-scan. Transition faults in the scan logic are considered as well. [ABSTRACT FROM AUTHOR]

This paper proposes a complete and full automation framework of evaluating design rules (DRs) to facilitate the process of design technology co-optimization (DTCO), which is highly demanded in 14-nm and beyond technologies. Our proposed framework explores the changes of DRs and evaluates the impacts on the number and types of DR violations as well as the resulting cell/chip layout area. Precisely, the core engine of our DR evaluation framework for DTCO, the automatic cell layout generator, consists of key enabling techniques for standard cell layout optimization. They are integrated coherently to seamlessly support the advanced process technologies using FinFET transistors, complex DRs, and double patterning (DP) lithography. Also, the tight integration of our automatic cell layout generation into the DR evaluation framework with diverse analysis features enables the DTCO process to be much faster and more efficient. We provide a set of experimental data not only to show how much our proposed enabling techniques are effective in optimizing layouts but also to show how effectively our framework explores and analyzes the DTCO parameters (e.g., ground DRs and DP DRs). [ABSTRACT FROM AUTHOR]

Leveraging the inherent error resilience of a large number of application domains, approximate computing is established as an efficient design alternative to improve their energy profile. In this brief, we design energy optimal cross-layer approximate arithmetic circuits by enabling the efficient application of voltage overscaling (VOS). Departing from the conventional approaches followed today, we introduce the voltage-driven functional approximation and present the VoltAge-Driven nEtlist pRuning (VADER) framework. VADER is an automated synthesis framework that can be seamlessly integrated in any hardware design flow and implements a voltage-driven gate-level netlist pruning. Experimental evaluation shows that VADER reduces the error of the VOS application by 52% on average and delivers on average designs with 34% higher energy savings compared to state-of-the-art approximate adders and multipliers. [ABSTRACT FROM AUTHOR]

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration random-access memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13- $\mu \text{m}$ CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three orders of magnitude. On the conditions of linear energy transfer being up to 14 MeV $\cdot$ cm2/mg, no SEU errors were observed from DFF in the hardened FPGA design. [ABSTRACT FROM AUTHOR]

Emerging physical unclonable function (PUF) circuit designs in the IC supply chain pose not only a challenge to security threats but also a serious concern about hardware efficiency. The existing conventional PUF methods extract intrinsic random physical variation to generate two-valued secret key bits, which lack logical complexity and have poor efficiency in interconnect lines. This paper proposes a multiple-valued logic PUF circuit (MPUF), which focuses on adding logical complexity and minimizing hardware cost by processing on multilevel-cell and interconnect lines. The twins’ cell is selected as the MPUF cell to source the multiple-valued physical variation, and the bit-line sharing strategy was integrated to implement the four-valued PUF data. After full-custom designing, the MPUF with 512 cells only needs 16 transmit bit lines. The proposed MPUF chip is fabricated under 65-nm CMOS technology and the core area occupies approximately 0.016 mm2 with a 4.9- $\mu \text{m}^{2}$ bitcell size. The measured results show that the MPUF data passed National Institute of Standards and Technology randomness tests, and that it operates 0.1-pJ/b energy efficiency at 1.2 V, ensures randomness and uniqueness with 50.42% hamming distance, and less than 0.04 autocorrelation at 95% confidence level. Compared with other state of the arts, logical complexity improves 50% for resisting power attacks. [ABSTRACT FROM AUTHOR]

In this paper, binary decision diagram (BDD)-based dual-rail precharge logic circuit schemes have been developed to counter differential power analysis attacks, timing attacks, and early propagation attacks. Different precharge logic schemes (top precharging, top–bottom precharging, bottom precharging, and symmetric nMOS bottom precharging) are presented and evaluated. The hallmark of our circuit schemes is that an identical number of switchings is ensured on each circuit path. The transistors are interconnected to create pull-up and pull-down paths to outputs by way of binary decisions based on the input variables, so as to realize the required Boolean function. A simple synthesis algorithm for mapping a given Boolean function to such a BDD-based circuit is also presented. Experimentation has been carried out on two 4-, 16-, 32-, and 64-bits S-boxes to establish resistance of our circuits to power analysis attack and to highlight the low-power characteristics with the help of attributes such as peak power variance, average power, propagation delay, normalized standard deviation of power, and normalized energy deviation. Differential power attacks such as difference of mean and correlation power analysis have been carried out. Resilience to the early propagation effect is also demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, the problem of determining the sensitization probability of a path by a test vector is investigated which is important when testing for delay defects due to process variations. An algorithm and its extension are presented with a tradeoff in accuracy and execution time. Gate delays are modeled as probability mass functions, and novel operations are introduced that take into consideration circuit reconvergences and path correlations. The proposed approach estimates accurately the sensitization probability of a path for a test vector. It relies on novel operations at each gate on the target path. Experimental results and comparisons with Monte Carlo are presented on the ISCAS’85, ISCAS’89, and ITC’99 benchmarks. [ABSTRACT FROM AUTHOR]

In this paper, a timing speculation technique with low-overhead in situ delay monitors placed along critical paths is presented. The proposed insertion of monitors enables timing error prevention within the same clock cycle. Compared to other techniques, the design cost per monitor in our technique is low because no additional gates for the guard banding, inspection window generation, and short path extension are required. We benchmarked our approach on an ARM Cortex M0. The insertion strategy reduces the number of monitors by up to $\sim 23\times $ , power by $\sim 5.5\times $ , and area by $\sim 2.8\times $ compared to the traditional in situ monitoring techniques that insert monitors at the flip-flops. The timing error correction uses a global clock stretching unit to prevent errors within one cycle. With the proposed error prevention technique, ~22% more delay variation is tolerated with a negligible energy overhead of less than ~1%. [ABSTRACT FROM AUTHOR]

Intervals between data items propagating in self-timed circuits are controlled by handshake signals rather than by a clock. In many self-timed designs, a trailing data item will catch up with a leading item or token, even when it trails by thousands of gate delays. This effect, called “drafting,” can be seen in many of the self-timed designs, e.g., GasP, Mousetrap, Click, and Micropipeline. Drafting occurs because the delay of a trailing token through a self-timed stage depends on how much earlier the leading token departed. Contrary to earlier work, we find the cause of drafting to be charge stored on an isolated node between two series transistors. This mechanism occurs in many decision gates that implement a logical AND. The charge on the floating internal node can drift between actions and thereby change the delay of the gate. Drafting behavior may be modulated by controlling the internal node of the GasP NOR gate. This offers possibilities for using self-timed circuits in applications where the interval between data items carries information, for instance, spiking neural networks, security, or real-time signal processing. [ABSTRACT FROM AUTHOR]

Three-Dimensional NAND flash technology is one of the most competitive integrated solutions for the high-volume massive data storage. So far, there are few investigations on how to use 3-D NAND flash for in-memory computing in the neural network accelerator. In this brief, we propose using the 3-D vertical channel NAND array architecture to implement the vector–matrix multiplication (VMM) with for the first time. Based on the array-level SPICE simulation, the bias condition including the selector layer and the unselected layers is optimized to achieve high computation accuracy of VMM. Since the VMM can be performed layer by layer in a 3-D NAND array, the read-out latency is largely improved compared to the conventional single-cell read-out operation. The impact of device-to-device variation on the computation accuracy is also analyzed. [ABSTRACT FROM AUTHOR]

Time borrowing techniques have been widely used to mitigate the timing errors in high-performance designs. A new dynamic flip-flop conversion technique is introduced by Ahmadi et al. (2015) which dynamically converts flip-flops into transparent latches to grant the time borrowing from the next stage and prevent setup time violation. However, it is not able to prevent the timing violation in the successive critical path (SCP) and critical feedback path (CFP) structures. In this brief, we introduce a novel idea of using the output of fast prediction logic of the critical path along with dynamic clock stretching in SCP and CFP structures. The results show that our technique, on average, is able to improve the performance by 20.2% and 14.8% during the prelayout and postlayout simulations, respectively. Furthermore, the proposed technique is almost 7.7% more effective in terms of the performance improvement with only 0.1% area overhead in comparison with the best existing technique. [ABSTRACT FROM AUTHOR]

This brief describes a new approach to test compaction under transparent scan. Transparent scan achieves higher levels of test compaction than possible with the conventional scan-based tests by interleaving scan shift cycles and functional clock cycles in arbitrary ways. Earlier approaches relied on the computation of a single transparent-scan sequence, and the omission of test vectors from it. However, a single transparent-scan sequence can be prohibitively long. In the approach described in this brief, a transparent-scan test set consists of several sequences whose lengths are limited. Test compaction is achieved by combining sequences into longer sequences that detect more faults, and removing from the test set entire sequences that become unnecessary. Experimental results for benchmark circuits demonstrate the ability of the procedure to achieve test compaction without creating prohibitively long transparent-scan sequences. [ABSTRACT FROM AUTHOR]

Counters are a generally useful circuit that appear in many contexts. Because of this, the design space for clocked counters has been widely explored. However, the same cannot be said for robust clockless counters. To resolve this, we designed an array of constant response time counters using the most robust clockless logic family, quasi-delay-insensitive (QDI) circuits. We compare our designs to their closest QDI counterparts from the literature, showing significant improvements in design quality metrics including transistor count, energy per operation, frequency, and latency in a 28-nm process. We also compare our designs against prototypical synchronous counters generated by commercial logic synthesis tools. [ABSTRACT FROM AUTHOR]

Memristor, which is a two-terminal nanodevice, widely used in various fields, e.g., machine learning and neuromorphic systems, has attracted much attention these years. Memristor can also be used to realize an implication logic gate and thus logic circuits. However, the fanouts in a memristor-based logic circuit have some constraints and need to be processed with special care. On the other hand, in addition to the number of memristors, the number of operational pulses is another metric to measure the quality of a memristor-based logic circuit. Hence, in this paper, we propose a synthesis algorithm to deal with the fanout problems in memristor-based logic circuits using implication logic gates for having a minimal number of operational pulses. We conducted experiments on a set of MCNC benchmarks. The experimental results show that the proposed algorithm can reduce 29% operational pulses and 36% memristor count on average compared with the state-of-the-art. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

Near threshold computing (NTC) systems have been inherently plagued with heightened process variation (PV) sensitivity. Choke points are an intriguing manifestation of this PV sensitivity. In this paper, we explore the probability of minimum timing violations, caused by choke points, in an NTC system, and their nontrivial impacts on the system reliability. We show that conventional timing error mitigation techniques are inefficient in tackling choke point-induced minimum timing violations. Consequently, we propose a comprehensive error mitigation technique, Trident, to tackle choke points at NTC. Trident offers a $1.37\times $ performance improvement and a $1.11\times $ energy-efficiency gain over Razor at NTC with minimal hardware and power overheads. [ABSTRACT FROM AUTHOR]

Fault diagnosis plays a major role in IC yield enhancement as it can help identify yield limiting defects in fabricated devices. The information on such defects is used to guide modifications to design and/or fabrication processes to improve yield. These steps may be iterated until acceptable yield levels are achieved. Due to circuit structure and limitations of the tests and/or diagnosis procedures used, after the application of tests and logic diagnosis, many detectable faults remain undistinguished from each other and are reported out as suspected defects, thus limiting diagnostic resolution and affecting ability to pinpoint yield limiting defects. This paper proposes a repair-for-diagnosis method to distinguish undistinguished fault pairs in logic circuits to improve diagnostic resolution and hence facilitate the determination of yield limiting defects. Even functionally equivalent faults which cannot be distinguished by any tests can be distinguished using the proposed method. The method proposed augments a circuit under consideration by adding redundant logic that allows repair of a fault to distinguish it from other faults in a group of undistinguished faults. Procedures to efficiently use the proposed repair strategy are given. Once the yield limiting defects are identified and corrective actions in the design and manufacturing process are done, the additional logic of repair-for-diagnosis can be deleted from the final design for volume production with desired yields. Experimental results on ISCAS-89 and IWLS05 benchmark circuits demonstrate the efficacy of the proposed method to improve diagnostic resolution. [ABSTRACT FROM AUTHOR]