Back to Search
Start Over
Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits.
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Aug2022, Vol. 30 Issue 8, p1073-1083, 11p
- Publication Year :
- 2022
-
Abstract
- The functionality of polymorphic circuits can be altered using a control variable. Owing to the multifunctional embodiment in polymorphic circuits, they are helpful to reconfigure circuit behavior from the gate level to the system level, either on the fly or off-line. The polymorphic circuit approaches available in the literature are either based on custom nonlinear circuit designs or special emerging devices, such as ambipolar FET and configurable magnetic devices. While some of these approaches are inefficient in performance, the other approaches involve exotic devices. We have proposed a novel polymorphic circuit design approach based on crosstalk (CT) computing, where we leverage deterministic signal interference between nanometal lines for logic computation and reconfiguration. In this article, we elaborate upon the polymorphic circuit design in CT computing through mathematical formulation, which conveys the rationale to generalize and achieve a wide variety of polymorphic circuits, and then demonstrate a comprehensive list of polymorphic circuit designs. In addition, all circuits are characterized and benchmarked against CMOS circuit implementations to gauge the benefits. Finally, we compare the CT polymorphic circuit approach with other approaches in the literature and highlight its unique features and limitations. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to CT computing, which leads to benefits in the circuit power, performance, and area (PPA). Our circuit designs, simulation, and PPA characterization results show that the polymorphic CT circuits provide $3\times $ improvement in transistor count, $2\times $ improvement in switching energy, and $1.5\times $ improvement in speed for polymorphic logic circuits. In the best-case, the transistor count reduction is $5\times $. [ABSTRACT FROM AUTHOR]
- Subjects :
- MAGNETIC devices
MINIMAL design
LOGIC circuits
TRANSISTORS
INTEGRATING circuits
Subjects
Details
- Language :
- English
- ISSN :
- 10638210
- Volume :
- 30
- Issue :
- 8
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publication Type :
- Academic Journal
- Accession number :
- 158185904
- Full Text :
- https://doi.org/10.1109/TVLSI.2022.3173344