Back to Search
Start Over
BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature.
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Nov2022, Vol. 30 Issue 11, p1677-1690, 14p
- Publication Year :
- 2022
-
Abstract
- This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processor’s multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature. [ABSTRACT FROM AUTHOR]
- Subjects :
- HIGH temperatures
INFORMATION modeling
TEMPERATURE distribution
LOGIC circuits
Subjects
Details
- Language :
- English
- ISSN :
- 10638210
- Volume :
- 30
- Issue :
- 11
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publication Type :
- Academic Journal
- Accession number :
- 160688021
- Full Text :
- https://doi.org/10.1109/TVLSI.2022.3186946