Search

This paper presents that advanced actively body-bias controlled (Advanced ABC) technology contributes to enhancing operation margins of static random access memory (SRAM). For the first time, significant enhancement of static noise margin (SNM) is successfully realized by using a body bias of load, access, and driver transistors while suppressing threshold-voltage variations. In this technology, well taps control the body potential of the load transistor and word lines also control the body potential of the access and driver transistors. It is demonstrated that the write and read margins of 65-nm-node silicon-on-insulator (SOI) SRAMs are improved by the Advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32 nm and 49% for 22 nm node. It is summarized that this technology is one of countermeasures for emerging generations.

An actively body-bias controlled (ABC) silicon-on-insulator (SOI) static random access memory (SRAM) connecting the bodies of the access and the driver transistors with the word line is proposed to realize high-speed and low-voltage operation. We developed the direct body contact to apply forward biases to the bodies without increases in the area penalty and the parasitic gate capacitance. An increase of the standby current does not occur because the body biases are not applied when the word-line voltage is low level. It is demonstrated that a significant speed improvement and a reduction of performance variations for the SRAM are achieved by applying the body bias. Neutron-accelerated soft-error tests reveal that the ABC structure suppresses soft-error events due to the body-tied SOI structure. In summary, the ABC SOI technology is one of the countermeasures for emerging generations.

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 /spl mu/m floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V/sub th/) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V/sub th/-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 /spl mu/m, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current.

A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, "substrate bias" is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits.

In this study we develop a strain distribution sensor to lift a object by fingers without producing whole slip or applying excessive force even when the weight and the friction coefficient of the object are unknown. Strain gages bonded on thin plates are arranged at even intervals inside an elastic finger having curved surface made of silicone rubber. Geometry of the elastic finger is designed by calculating the contact condition between the finger and a plate with/without tangential load using a FE (finite element) analysis. We also measured the characteristics of the strain distribution sensor. Results show that the grip force can be controlled using the designed strain distribution sensor.

A reliable tantalum (Ta)-gate device technology, which can drastically reduce the number of process steps, has been developed. Ta-gate fully-depleted-silicon-on-insulator (FDSOI) MOSFETs with 0.15-/spl mu/m gate length by low-temperature processing below 500/spl deg/C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta-gate MOSFETs in the deep-submicrometer regime is provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. In the guideline, the recrystallization of the source/drain region gives inferior limits of the SOI thickness and the process temperature. Thermal reaction between Ta and SiO/sub 2/ films sets a superior limit of the process temperature, and a short-channel effect sets a superior limit of the SOI thickness.

The threshold voltages of thin-film fully-depleted silicon-on-insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta) as the gate materials. Ta-gate FDSOI MOSFET's have excellent threshold voltage control for 1.0 V application on low impurity concentration SOI layers in both nMOS and pMOS. The low-temperature processing after the gate oxidation step leads to good on/off characteristics in Ta-gate SOI MOSFET's because of no reaction between Ta gate electrode and SiO/sub 2/ gate insulator. This technology makes it possible to drastically decrease the number of the process steps for CMOS fabrication, because the same gate material is available for both nMOS and pMOS.

Dynamic force spectroscopy (DFS) based on atomic force microscopy, which enables us to obtain information on the interaction potential between molecules such as antigen–antibody complexes at the single-molecule level, is a key technique for advancing molecular science and technology. However, to ensure the reliability of DFS measurement, its basic mechanism must be well understood. We examined the effect of the molecular linker used to fix the target molecule to the atomic force microscope cantilever, i.e., the force direction during measurement, for the first time, which has not been discussed until now despite its importance. The effect on the lifetime and barrier position, which can be obtained by DFS, was found to be ∼10 and ∼50%, respectively, confirming the high potential of DFS.

A statistical compact RTN (Random Telegraph Noise) model with a fixed V th shift and V gs dependent trap time constants is proposed. It accurately reproduces the experimental observation of larger V th fluctuation at higher |V gs |. The model is also applied to analysis of SRAM V min fluctuation and finds out the distribution follows a log-normal statistics.

Voltage and technology scaling and increasing random variation in MOSFET characteristics reduce the operational margin of SRAM functionality, and several design techniques have been suggested to improve margins [1–3]. However, it is still difficult to achieve low-voltage operation (less than 1V) by design alone for devices such as sensor network applications using solar batteries. Design solutions combined with device techniques are required for robust SRAM operation and at the same time maintain low standby leakage.

This paper presents that advanced actively body-bias controlled (Advanced ABC) technology contributes to enhancing operation margins of SRAMs. Significant enhancement of static noise margin (SNM) is successfully realized by using a body bias of load transistors while suppressing threshold-voltage variations for the first time. It is demonstrated that the write and read margins of 65nm-node SOI SRAMs are improved by the advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32nm and 49% for 22nm node. It is summarized that this technology is one of countermeasures for emerging generations.

This paper describes the experimental characteristics of RF components with layout and structural optimization, fabricated in 0.10-/spl mu/m 1.2-V SOI-CMOS technology with partial trench isolation (PTI). ESD protection-grounded gate SOI-NMOSFETs achieve high reliability due to body-tied structure with PTI, and newly proposed ESD diodes also derive superior performance. Moreover, this technology offers a low loss RF switch and a broadband amplifier with low power consumption. These results are very promising for the fabrication of broadband RF integrated circuits.

As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesn't need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.

Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure including connections of the access and the driver transistor's bodies to the word line is proposed to realize low-voltage operation. We developed the direct body contact technology to apply forward biases to the bodies without area penalties and increases of parasitic gate capacitances by using the hybrid trench isolation for the first time. Moreover, the standby current does not change because the body bias is not applied when the word-line voltage is low level. It is successfully demonstrated that low-voltage and high-speed operation is achieved by using the ABC SOI SRAM.

A reliable tantalum (Ta) gate device technology, which can drastically reduce the number of process steps, has been developed. Ta gate Fully-Depleted-Silicon-On-Insulator (FDSOI) MOSFETs with 0.15 /spl mu/m gate length by low-temperature processing below 500/spl deg/C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta gate MOSFETs in the deep-submicron regime are provided by investigating a wide range of performance and reliability constraints on the process temperature and the SOI thickness. For low-temperature processing, there is the lower limit of the SOI thickness which is given by the recrystallization of the source/drain layer.

We achieved 135 GHz f/sub max/ and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V/sub th/ variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

In this paper, for the first time, we propose a 0.18/spl mu/m SOI CMOS using hybrid trench isolation with high resistivity substrates (HRS) and reveal its impact on high performance embedded RF/analog applications, which is essential for "system on a chip (SOC)". The hybrid trench isolation is a type of partial trench isolation which serves scalable body-tied SOI MOSFETs, and full trench isolation which provides high quality passives associated with the HRS. Using this technology, the advantages of SOI MOSFETs are quantitatively proven. Excellent body-fixing capability of this SOI MOSFET, and high-quality on-chip inductance is demonstrated for RF/analog LSIs. For mixed-signal configurations, superior CMOS performance is demonstrated.

Reliability against radiation is an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long channel regime. In transistors with a channel length of 0.18 µm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0 µm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment.