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1. Novel Mixed Design of Tone Mapping Technique for HDR CMOS Image Sensor

Author: TIMA ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire de psychologie et neurocognition (LPNC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Université Pierre-Mendès-France - Grenoble II, Abbas, H., Amhaz, H., Alleysson, David, Sicard, G., TIMA ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire de psychologie et neurocognition (LPNC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Université Pierre-Mendès-France - Grenoble II, Abbas, H., Amhaz, H., Alleysson, David, and Sicard, G.
Abstract: ISBN : 978-1-4799-3569-7, International audience, In this paper we present a new mixed design of the tone mapping technique used to adjust high dynamic range (HDR) image sensor luminosities. The dynamic range extension along with the tone mapping technique implementation allows covering correctly more than six orders of luminosity magnitude. The architecture is inspired from the human vision system operation. The proposed function and its architecture design as well as MATLAB emulation applied to images extracted from a linear CMOS image sensor designed in 0.35um AMS technology are illustrated along the paragraphs of the paper.

2. A built-in multi-mode stimuli generator for analogue and mixed-signal testing

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), DELET, Univ. Fed. do Rio Grande do Sul (UFRGS) ; Univ. Fed. do Rio Grande do Sul, SysMic ; Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM) ; CNRS - Université Montpellier II - Sciences et techniques - CNRS - Université Montpellier II - Sciences et techniques - Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - DELET, Univ. Fed. do Rio Grande do Sul (UFRGS) ; Univ. Fed. do Rio Grande do Sul - Univ. Fed. do Rio Grande do Sul, Lubaszewski, M., Renovell, M., Mir, S., Azaïs, Florence, Bertrand, Y., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), DELET, Univ. Fed. do Rio Grande do Sul (UFRGS) ; Univ. Fed. do Rio Grande do Sul, SysMic ; Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM) ; CNRS - Université Montpellier II - Sciences et techniques - CNRS - Université Montpellier II - Sciences et techniques - Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - DELET, Univ. Fed. do Rio Grande do Sul (UFRGS) ; Univ. Fed. do Rio Grande do Sul - Univ. Fed. do Rio Grande do Sul, Lubaszewski, M., Renovell, M., Mir, S., Azaïs, Florence, and Bertrand, Y.
Abstract: Among other applications, programmable oscillators are used to generate patterns for analogue and mixed-signal built-in self-test. The switched-capacitor multi-mode stimuli generator presented in this work associates programmability with lower area overheads. The type of signal (pulse, ramp or sinewave), the amplitude and the frequency of oscillation can be easily programmed. The stimuli generator is expected to alleviate surface penalties, because digital programming of the oscillation frequency can be achieved by changing the switching frequency using an embedded frequency divider. Experimental results involving a biquad filter show that a very high fault coverage can be obtained in both transient and multifrequency modes of the stimuli generator

3. Evaluation d'un BIST d'un capteur de vision CMOS à base d'une copule non Gaussienne

Author: LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, K., Bounceur, Ahcène, Mir, S., Euler, Reinhardt, LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, K., Bounceur, Ahcène, Mir, S., and Euler, Reinhardt
Abstract: National audience, L'évaluation des techniques de test analogique/RF nécessite une précision du modèle statistique multivarié des paramètres de sorties du dispositif sous test, à savoir les performances et les mesures de test. Un modèle basé sur les copules sépare les dépendances entre ces paramètres de sortie et leurs distributions marginales, fournissant un ensemble complet permettant de modéliser les dépendances en utilisant des lois statistiques multivariées usuelles. Dans cet article, nous utiliserons la théorie des copules pour estimer un tel modèle et nous montrerons comment utiliser les copules Archimédiennes afin de modéliser des dépendances non Gaussiennes. En particulier, la copule de Clayton sera utilisée pour modéliser les dépendances entre les paramètres de sorties d'un capteur de vision CMOS dans le but d'évaluer son BIST.

4. Novel Mixed Design of Tone Mapping Technique for HDR CMOS Image Sensor

Author: TIMA ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire de psychologie et neurocognition (LPNC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Université Pierre-Mendès-France - Grenoble II, Abbas, H., Amhaz, H., Alleysson, David, Sicard, G., TIMA ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire de psychologie et neurocognition (LPNC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Université Pierre-Mendès-France - Grenoble II, Abbas, H., Amhaz, H., Alleysson, David, and Sicard, G.
Abstract: ISBN : 978-1-4799-3569-7, International audience, In this paper we present a new mixed design of the tone mapping technique used to adjust high dynamic range (HDR) image sensor luminosities. The dynamic range extension along with the tone mapping technique implementation allows covering correctly more than six orders of luminosity magnitude. The architecture is inspired from the human vision system operation. The proposed function and its architecture design as well as MATLAB emulation applied to images extracted from a linear CMOS image sensor designed in 0.35um AMS technology are illustrated along the paragraphs of the paper.

5. Novel Auto-Adaptative Integration-Time Technique for CMOS Image Sensor

Author: TIMA ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire de psychologie et neurocognition (LPNC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Université Pierre-Mendès-France - Grenoble II, Abbas, H., Amhaz, H., Alleysson, David, Sicard, G., TIMA ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire de psychologie et neurocognition (LPNC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Université Pierre-Mendès-France - Grenoble II, Abbas, H., Amhaz, H., Alleysson, David, and Sicard, G.
Abstract: International audience, In this paper, we present a novel technique developed in order to extend the dynamic range of a linear CMOS image sensor. This technique allows covering all the range of luminosities by auto-choosing the appropriate integration time. The proposed system is inspired form the human vision where we mimic the neural photoreceptor adaptation. The emulation results of the MATLAB model are shown to validate our approach.

6. Evaluation d'un BIST d'un capteur de vision CMOS à base d'une copule non Gaussienne

Author: LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, Kamel, Bounceur, Ahcène, Mir, Salvador, Euler, Reinhardt, LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, Kamel, Bounceur, Ahcène, Mir, Salvador, and Euler, Reinhardt
Abstract: National audience, L'évaluation des techniques de test analogique/RF nécessite une précision du modèle statistique multivarié des paramètres de sorties du dispositif sous test, à savoir les performances et les mesures de test. Un modèle basé sur les copules sépare les dépendances entre ces paramètres de sortie et leurs distributions marginales, fournissant un ensemble complet permettant de modéliser les dépendances en utilisant des lois statistiques multivariées usuelles. Dans cet article, nous utiliserons la théorie des copules pour estimer un tel modèle et nous montrerons comment utiliser les copules Archimédiennes afin de modéliser des dépendances non Gaussiennes. En particulier, la copule de Clayton sera utilisée pour modéliser les dépendances entre les paramètres de sorties d'un capteur de vision CMOS dans le but d'évaluer son BIST.

7. Evaluation d'un BIST d'un capteur de vision CMOS à base d'une copule non Gaussienne

Author: LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, K., Bounceur, Ahcène, Mir, S., Euler, Reinhardt, LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, K., Bounceur, Ahcène, Mir, S., and Euler, Reinhardt
Abstract: National audience, L'évaluation des techniques de test analogique/RF nécessite une précision du modèle statistique multivarié des paramètres de sorties du dispositif sous test, à savoir les performances et les mesures de test. Un modèle basé sur les copules sépare les dépendances entre ces paramètres de sortie et leurs distributions marginales, fournissant un ensemble complet permettant de modéliser les dépendances en utilisant des lois statistiques multivariées usuelles. Dans cet article, nous utiliserons la théorie des copules pour estimer un tel modèle et nous montrerons comment utiliser les copules Archimédiennes afin de modéliser des dépendances non Gaussiennes. En particulier, la copule de Clayton sera utilisée pour modéliser les dépendances entre les paramètres de sorties d'un capteur de vision CMOS dans le but d'évaluer son BIST.

8. Evaluation d'un BIST d'un capteur de vision CMOS à base d'une copule non Gaussienne

Author: LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, Kamel, Bounceur, Ahcène, Mir, Salvador, Euler, Reinhardt, LAB-STICC_UBO_CACS_CS ; Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Lab-STICC_UBO_CACS_MOCS ; Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Lab-STICC_UBO_CACS_MOCS ; Université de Bretagne Occidentale - UFR Sciences et Techniques - Département Informatique (UBO UFR ST) ; Université de Bretagne Occidentale (UBO) - Université de Bretagne Occidentale (UBO) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - CNRS - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) ; CNRS - Université de Bretagne Occidentale (UBO) - Université de Bretagne Sud (UBS) - Télécom Bretagne - Institut Supérieur des Sciences et Technologies de Brest (ISSTB) - ENSTA Bretagne - Institut Mines-Télécom - PRES Université Européenne de Bretagne (UEB) - Ecole Nationale d'Ingénieurs de Brest - CNRS - ENSTA Bretagne - Ecole Nationale d'Ingénieurs de Brest, Beznia, Kamel, Bounceur, Ahcène, Mir, Salvador, and Euler, Reinhardt
Abstract: National audience, L'évaluation des techniques de test analogique/RF nécessite une précision du modèle statistique multivarié des paramètres de sorties du dispositif sous test, à savoir les performances et les mesures de test. Un modèle basé sur les copules sépare les dépendances entre ces paramètres de sortie et leurs distributions marginales, fournissant un ensemble complet permettant de modéliser les dépendances en utilisant des lois statistiques multivariées usuelles. Dans cet article, nous utiliserons la théorie des copules pour estimer un tel modèle et nous montrerons comment utiliser les copules Archimédiennes afin de modéliser des dépendances non Gaussiennes. En particulier, la copule de Clayton sera utilisée pour modéliser les dépendances entre les paramètres de sorties d'un capteur de vision CMOS dans le but d'évaluer son BIST.

9. 'Lateral Field Excitation of thickness shear modes in an AlN membrane'

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire des technologies de la microélectronique (LTM) ; CNRS - Université Joseph Fourier - Grenoble I, Laboratoire d'Electronique et des Technologies de l'Information (LETI) ; CEA, RFM ; Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Gorisse, M., Bertaud, T., Reinhardt, A., Borel, M., Billard, C., Defaÿ, E., Lacrevaz, T., Bermond, C., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Laboratoire des technologies de la microélectronique (LTM) ; CNRS - Université Joseph Fourier - Grenoble I, Laboratoire d'Electronique et des Technologies de l'Information (LETI) ; CEA, RFM ; Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC) ; CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG) - CNRS - Université de Savoie - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Gorisse, M., Bertaud, T., Reinhardt, A., Borel, M., Billard, C., Defaÿ, E., Lacrevaz, T., and Bermond, C.
Abstract: International audience

10. Analysis of defect tolerant crossbar network implementations [MCM]

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, Inst. Nat. Polytech. de Grenoble, France (CSI) ; Institut National Polytechnique de Grenoble (INPG), Leveugle, R., Brahic, P., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, Inst. Nat. Polytech. de Grenoble, France (CSI) ; Institut National Polytechnique de Grenoble (INPG), Leveugle, R., and Brahic, P.
Abstract: ISBN: 9985590813, This paper deals with the implementation of crossbar-like networks in active substrates of MCMs. Such networks are essentially used in parallel computing, but can also be implemented to improve the observability of internal nodes. It is shown that the manufacturing yield can be significantly increased when using a redundant network architecture. The impact of the main parameters is analyzed and it is shown in particular that the ratio between the defect densities of the interconnection lines and of the active elements has a very strong impact.

11. Zero-defect designs, why and how: formal verification vs. automated synthesis

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Politecnico di Torino [Torino] (Polito) ; Politecnico di Torino, Borrione, D., Prinetto, P., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Politecnico di Torino [Torino] (Polito) ; Politecnico di Torino, Borrione, D., and Prinetto, P.
Abstract: ISBN: 0444880151, Zero-defect VLSI design is a goal one must try to reach and CAD tools provide an increasingly important support to designers. High-level automated synthesis and formal verification are cooperating approaches to this end. The paper analyzes the general framework of digital design and the relationships between synthesis and verification as far as functional correctness is concerned, showing their limits, mutual dependencies, and how they can and should work together.

12. Design and test of next generation integrated systems embedding MEMS

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Mir, S., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Mir, S.
Abstract: This paper presents an overview of microelectromechanical systems (MEMS) research topics. Manufacturing technologies, including bulk and surface micromachining, are illustrated using fabricated devices. Optimal exploitation of these technologies relies on the integration in a single chip of MEMS parts with their electronic interfaces. Current challenges for bringing the analysis, design and test of these new generation of devices in line with microelectronics are then discussed.

13. Delay directed adder synthesis and optimization

Author: Technical University of Sofia (TUS) ; Technical University of Sofia, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Tchoumatchenko, V., Vassileva, T., Guyot, A., Technical University of Sofia (TUS) ; Technical University of Sofia, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Tchoumatchenko, V., Vassileva, T., and Guyot, A.
Abstract: This paper present a new approach to timing driven optimization of adders. An algorithm for the optimum transistor sizing of a class of fast adders with respect to the user performance specifications is presented. A sizing strategy is derived from a simple delay model. The optimization procedure and the sizing strategy can be used for several adders architectures.

14. Efficient implementations of self-checking adders and ALUs

Author: iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Nicolaidis, M., iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Nicolaidis, M.
Abstract: ISBN: 0818636807, The author presents efficient self-checking implementations for adders and ALUs (ripple carry, carry lookahead, carry skip schemes). Among all the known self-checking adders and ALUs the parity prediction scheme has the advantage to require the minimum overhead for the adder/ALU and the minimum overhead for the other data path blocks. It has also the advantage to be compatible with memory systems checked by parity codes. The drawback of this scheme is that it is not fault secure even for single stuck-at faults. The new designs require lower overhead than the above scheme and also they have all the other advantages of this scheme. In addition the new schemes are strongly fault secure or totally self-checking for a comprehensive fault model which includes stuck-at, stuck-on and stuck open faults. Thus, the new schemes are substantially better than any other known scheme.

15. Built-in concurrent checking of ASICs

Author: CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Delord, X., Leveugle, R., Saucier, G., CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Delord, X., Leveugle, R., and Saucier, G.
Abstract: This paper focuses on the implementation on silicon of concurrent test facilities in ASICs. The concurrent checking method employed here is based on signature analysis because of its global low cost (hardware, area, complexity, . . .) and its high detection capability. Details on signature analysis and instruction flow compaction are recalled and two applications are given. The former is the actual implementation of this principle in an application specific microprocessor and the later extends it to dedicated controllers. For dedicated controllers, two approaches are presented. The first one applies the machine level approach to a lower level. The second one is very original as it takes profit of the synthesis of the controller to introduce checking capabilities nearly without overhead.

16. Analytical testing of data processing sections of integrated CPUs

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Courtois, B., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Courtois, B.
Abstract: Deals with analytical testing of circuits, i.e. testing depending on the physical (and not logical) structure of circuits. Fault hypotheses concerning contacts, metallizations, etc... are made. Successively, a stage of an elementary adder, an elementary adder, a stage of the M6800 ALU and the M6800 ALU are addressed. Other typical circuits of data processing sections of CPUs are evoked. Finally the implementation of algorithms for the entire data processing section of the M6800 is evoked, together with further development.

17. Re-engineering hardware specifications by exploiting design semantics

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Dept. of Comput. Sci., Manchester Univ., UK (DEPT. OF COMPUT. SCI., MANCHESTER UNIV., UK) ; University of Manchester, Mir, S., Filer, N.-P., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Dept. of Comput. Sci., Manchester Univ., UK (DEPT. OF COMPUT. SCI., MANCHESTER UNIV., UK) ; University of Manchester, Mir, S., and Filer, N.-P.
Abstract: ISBN: 0897916859, An Artificial Intelligence (AI) approach to re-engineering hardware specifications is presented in this paper. Knowledge about the functionality and purpose of the cells and signals of a design is automatically abstracted away from the specification. A heuristic analysis which exploits implicit design semantics is carried out. Examples of using the knowledge derived for enhancing the capabilities of ECAD frameworks and systems are provided.

18. Spread and folded architectures for FFT

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), VACHER, A., Guyot, A., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), VACHER, A., and Guyot, A.
Abstract: ISBN: 0818669853, Computing a Fourier transform with a parallel architecture of serial operators needs a lot of implementation area to obtain the high performances promised with this method. Allocating processors to each step of the computation or computing only one step at the same time is one of the problems to solve. The degree of integration of up-to-date chips promises a realistic implementation of such solutions. Accuracy, area, computation time are the parameters to study before choosing a method in relation to the number of samples of the working space.

19. Efficient UBIST implementation for microprocessor sequencing parts

Author: iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Nicolaidis, M., iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Nicolaidis, M.
Abstract: ISBN: 081869064X, An improved self-checking solution for the sequencing part of the MC 68000 microprocessor is presented. Compared with previous self-checking schemes for this microprocessor, the present scheme makes its possible to reduce the overhead and simplifies the implementation of both functional circuits, and checkers. The unified BIST (built-in self-test) method is applied to this scheme. This method uses a merging of self-checking and BIST techniques and allows a high fault coverage for all tests needed for integrated circuits, e.g., offline test (design verification, manufacturing, and maintenance test) and online concurrent error detection. An area overhead of about 27% is required, which is quite satisfactory in comparison with previous results.

20. An application specific microprocessor with two-level built-in control flow checking capabilities

Author: CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Michel, T., Leveugle, R., Gaume, F., Roane, R., CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Michel, T., Leveugle, R., Gaume, F., and Roane, R.
Abstract: ISBN: 0818628456, Concurrent checking consists of permanently verifying the behavior of a system by checking significant invariant properties to detect with a short latency either permanent or transient faults. Several types of methods have been proposed. The authors consider here control flow checking applied to microprocessor-based systems. Control flow invariant properties can be defined to verify the sequencing in the control part of the microprocessor, or the application program execution. Control flow checking has been implemented at these two levels in an application specific 32-bit microprocessor designed in the CMOS 1.5 mu technology from VLSI Technology. This processor, partly designed within a VLSI student project, is being manufactured by the French Multi Project organization.

21. Design methodology of FSMs with intrinsic fault tolerance and recovery capabilities

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), SEXTANT Avionique ; sextant, Leveugle, R., Martinez, L., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), SEXTANT Avionique ; sextant, Leveugle, R., and Martinez, L.
Abstract: ISBN: 0818628456, When ASICs are dedicated to highly dependable applications, concurrent checking and/or fault-tolerance capabilities are necessary on chip. In particular, FSMs must be protected against permanent and transient faults. The authors review the main proposals one can fine on this subject in the literature. Then, an approach is proposed to achieve intrinsic fault tolerance. This approach is based on a specific logic synthesis for FSMs described by their state transition graph.

22. PREVAIL: a proof environment for VHDL descriptions

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), LIM, Université de Provence (LIM) ; Université de Provence - Aix-Marseille I, Computer & Systems Dept., Ain Shams Univ., Egypt (COMPUTER & SYSTEMS DEPT., AIN SHAMS UNIV., EGYPT) ; Ain Shams Univiversity, Borrione, D., Pierre, L., Salem, A., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), LIM, Université de Provence (LIM) ; Université de Provence - Aix-Marseille I, Computer & Systems Dept., Ain Shams Univ., Egypt (COMPUTER & SYSTEMS DEPT., AIN SHAMS UNIV., EGYPT) ; Ain Shams Univiversity, Borrione, D., Pierre, L., and Salem, A.
Abstract: ISBN: 0444893679, The authors describe a formal verification environment for proving the equivalence of two VHDL architectures of the same design entity, provided the designer conforms to some restrictions in the description style. For simple bit-level combinational descriptions, the environment calls upon a tautology checker. For parameterized repetitive structures, and designs described at a more abstract level, the descriptions are translated into recursive functions, according to pre-defined templates, and a theorem is generated in a form acceptable by the Boyer-Moore theorem prover. For well identified classes of circuits, the proof is fully automatic.

23. A tool for automatic generation of BISTed and transparent BISTed RAMs

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Kebichi, O., Nicolaidis, M., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Kebichi, O., and Nicolaidis, M.
Abstract: ISBN: 0818631104, An efficient BIST architecture for RAMs that is based on M. Marinescu's (1982) algorithm is presented. This architecture considers the different levels of hierarchy of the algorithm and uses a block to implement each level of this hierarchy. Efficient implementations for these blocks are given. A transparent BIST technique, i.e., a BIST technique that preserves the initial contents of the RAM, is also presented, and an efficient transparent BIST architecture for RAMs is proposed. A tool allowing the automatic generation of BISTed and transparent BISTed RAMs is given. This generator is developed around the CADENCE CAD tools and uses the ES2 SOLO2030 standard cell library (CMOS 1.2 mu m).

24. Automatic generation of microprocessor test programs

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Bellon, C., Velazco, R., Liothin, A., Sadier, S., Saucier, G., Grillot, F., Issenman, M., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Bellon, C., Velazco, R., Liothin, A., Sadier, S., Saucier, G., Grillot, F., and Issenman, M.
Abstract: Presents an automatic generation system for behavioral test programs of microprocessors. First, the test environment is presented, as well as its consequences on test program generation. In the second part, the test principles are outlined; it is a behavioral test, i.e. a test determined from the user's description of the microprocessor; the resulting test programs are quite modular. The third part presents the description language and the generation system.

25. A low-power differential cross-coupled FET logic for GaAs asynchronous design

Author: Univ. Federal do Rio Grande do Sul ; Univ. Federal do Rio Grande do Sul, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Ribas, R.P., Bernal, A., Guyot, A., Univ. Federal do Rio Grande do Sul ; Univ. Federal do Rio Grande do Sul, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Ribas, R.P., Bernal, A., and Guyot, A.
Abstract: This paper describes a new GaAs MESFET structure, differential cross-coupled FET logic (DC/sup 2/FL), which is compatible with DCFL, DPTL and DCVS circuits. It can be efficiently used in delay-insensitive asynchronous circuits and self-timed rings, as well as in synchronous ones. When combined with the aforementioned differential structures, it offers attractive power savings without performance degradation. As an example, a fully functional 8-bit ripple carry adder has been designed and fabricated, verifying the expected very low power dissipation during the standby state.

26. ASPRO: an asynchronous 16-bit RISC microprocessor with DSP capabilities

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Telecom - CNET (CNET) ; France Télécom, Renaudin, M., Vivet, P., Robin, F., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Telecom - CNET (CNET) ; France Télécom, Renaudin, M., Vivet, P., and Robin, F.
Abstract: This paper describes a CMOS standard-cell quasi-delay-insensitive (QDI) 16-bit asynchronous microprocessor. ASPRO is a scalar microprocessor which issues instructions in-order and completes their execution out-of-order. Designed for embedded applications, it can be customized both at the hardware and software levels to fit specific application requirements. To demonstrate this feature, the prototype includes a multiplier-accumulator unit. Fabricated using the STMicroelectronics 0.25 mu m, 5-metal layer CMOS technology, ASPRO was found to be functional at first silicon, and runs at 140 peak MIPS. This project demonstrates that the methodology and the asynchronous logic are mature for the design of complex and fast fully asynchronous circuits.

27. A new contactless smartcard IC using an on-chip antenna and an asynchronous micro-controller

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Télécom Recherche & Développement (FT R&D) ; France Télécom, Abrial, A., Bouvier, J., Renaudin, M., Senn, P., Vivet, P., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), France Télécom Recherche & Développement (FT R&D) ; France Télécom, Abrial, A., Bouvier, J., Renaudin, M., Senn, P., and Vivet, P.
Abstract: A new generation of Contactless Smartcard Chip is described. The Contactless Smartcard Chip integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous Quasi Delay Insensitive (QDI) 8-bit micro-controller. Beyond the contactless smartcard application field, this new chip demonstrates that System-on-Chip integrating power reception and management, radio-frequency communication and signal processing are feasible. The chip associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS 6 metal layers .25µm technology from STMicroelectronics.

28. VLSI design of on-line add/multiply algorithms

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Skaf, A., Guyot, A., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Skaf, A., and Guyot, A.
Abstract: ISBN: 0818642300, We present some VLSI structures suitable for online arithmetic embedded algorithms using a radix-two fixed point signed digit system. As an application, we present online add/multiply architectures allowing the obtention of a zero-delay operator. An example of a circuit for online computation of several real functions using polynomials is also discussed.

29. Finitely self-checking circuits and their application on current sensors

Author: iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Nicolaidis, M., iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Nicolaidis, M.
Abstract: ISBN: 0818638303, The theory of digital self-checking circuits has been developed in order to make formal the techniques of designing digital circuits allowing one to ensure on-line concurrent error detection. In recent years analog and mixed signal circuits have gained importance and represent a relevant part of the products of the integrated circuits industry. The design of self-checking analog and mixed signals circuits is a potential solution in order to achieve the reliability of systems using such circuits. Thus, establishing the self-checking theory for analog and mixed signal circuits will allow one to make the design of such circuits formal, and is of great importance. This paper proposes the basic theory of self-checking analog and mixed signal circuits and applies this theory to the case of current checkers which should become in the future an important element for high quality manufacturing, testing and on-line concurrent error detection.

30. Datapath implementation: bit-slice structure versus standard cells

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Thomson Composants Militaires et Spatiaux ; Thomson, Leveugle, R., Safinia, C., Magarshack, P., Sponga, L., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Thomson Composants Militaires et Spatiaux ; Thomson, Leveugle, R., Safinia, C., Magarshack, P., and Sponga, L.
Abstract: ISBN: 0818628456, In some CAD systems, the implementation of regular or semi-regular datapaths is eased by providing specific tools, called `datapath compilers'. These tools take profit from the regularity in the datapath specification and generally use a bit-slice structure for the implementation. In other systems, no specific tool is provided and the datapaths are implemented using classical standard cell or block place and route tools. This paper proposes a framework for both evaluating the interest of using datapath compilers and comparing the effectiveness of different tools. Then, some experiments on commercially available datapath compilers demonstrate that a standard cell implementation is less efficient, at least for two-level metal technologies.

31. Design and comparison of GaAs and CMOS redundant divider

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Moussa, I., Guyot, A., Rost, P., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Moussa, I., Guyot, A., and Rost, P.
Abstract: This paper presents a combinatorial circuit for fast division Q:=A/D. High speed is achieved thanks firstly to an improved algorithm and secondly to its realization in gallium arsenide. An n bit divider produces an n bit quotient Q in 9*n NOR-gate-delays with n/sup 2/ add/subtract cells (called tail) controlled by n controllers (called head). The implementation of the divider circuit has been achieved by using buffering techniques and a full custom layout methodology that are well suited for high performance designs in GaAs direct-coupled FET logic (DCFL). Comparison of GaAs and CMOS implementations are given.

32. Svoboda-Tung division with no compensation

Author: France Télécom Recherche et Développement (FTR&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Montalvo, L.-A., Guyot, A., France Télécom Recherche et Développement (FTR&D) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Montalvo, L.-A., and Guyot, A.
Abstract: ISBN: 0818669055, The development of a new general radix-b division algorithm, based on the Svoboda-Tung division, suitable for VLSI implementation is presented. The new algorithm overcomes the drawbacks of the Svoboda-Tung techniques that have prevented the VLSI implementation. First of all, the proposed algorithm is valid for any radix b>or=2; and next, it avoids the possible compensation due to overflow on the iteration by re-writing the two most significant digits of the remainder. An analysis of the algorithm shows that a known radix-2 and two recently published radix-4 division algorithms are particular cases of this general radix-b algorithm. Finally, since the new algorithm is valid only for a reduced range of the IEEE normalised divisor, a pre-scaling technique, based on the multiplication of both the operands by a stepwise approximation to the reciprocal of the divisor is also presented.

33. Standard and ROM-based synthesis of FSMs with control flow checking capabilities

Author: CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Wending, X., Rochet, R., Leveugle, R., CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Wending, X., Rochet, R., and Leveugle, R.
Abstract: ISBN: 0818673044, This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow.

34. Hardware and software tools for microprocessor functional test

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Bellon, C., Velazco, R., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Bellon, C., and Velazco, R.
Abstract: The GAPT project (automatic generation of test programs for microprocessors) is in its final phase. The various components of the project (method, software tools and hardware environment) are presented. A behavioral test method of programmable circuits based on the notion of behavioral sequential machine and the identification principle is proposed. A system for automated generation of microprocessor test programs has been realized: starting from a concise description of the microprocessor, GAPT generates the test programs in assembly languages and the successive signal configurations. Using GAPT, the test program of a microprocess can be generated within a few weeks. A specific test environment has been designed and realized: it allows automatic test program generation and is able to handle large test programs; thus the duration is not prohibitive (according to the chosen option, the test duration is from a few seconds to a few minutes for a MC68000).

35. A methodology for on-line testing of microprocessors

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Courtois, B., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Courtois, B.
Abstract: A methodology for on-line testing of microprocessors without using massive redundancy is developed. This methodology includes different steps in order to determine the main parameter: the distribution of the detection time. These steps involve latency times evaluation, modeling, functional testing, LSI-MOS circuits testing and optimization problems. The methodology has been entirely applied to the Motorola 6800 and numerical results for that microprocessor are given.

36. A dedicated circuit for charged particles simulation using the Monte Carlo method

Author: Laboratoire de Physique des Composants à Semiconducteurs (LPCS) ; CNRS - École Nationale Supérieure d'Électronique et de Radioélectricité de Grenoble (ENSERG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Negoi, A., Guyot, A., Zimmerman, J., Laboratoire de Physique des Composants à Semiconducteurs (LPCS) ; CNRS - École Nationale Supérieure d'Électronique et de Radioélectricité de Grenoble (ENSERG), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Negoi, A., Guyot, A., and Zimmerman, J.
Abstract: ISBN: 081867959X, We present a dedicated integrated circuit for the simulation of charged particles based on Monte Carlo method. The Monte Carlo method leads to the solution of a particular form of the integro-differential Boltzmann equation (non-linear charge transport in semiconductors) permitting a direct statistical computation of the simulated particles distribution function in the phase space. This circuit should be the building block of a semiconductor device hardware simulator. Because of the complexity of microdynamical transport in semiconductors, the physical model used needs to be simplified in order to achieve a more simple circuit of small size. Starting from a chosen model we describe here how all the arithmetics involved in the problem has been set up for resolving the Boltzmann equation. Moreover, the binary format for the various physical quantities involved is discussed in view of the desired result accuracy: mainly, the drift velocity in a static uniform electric field taking into account all hot carrier effects.

37. A VLSI implementation of parallel fast Fourier transform

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), VACHER, A., Benkhebbab, M., Guyot, A., Rousseau, T., Skaf, A., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), VACHER, A., Benkhebbab, M., Guyot, A., Rousseau, T., and Skaf, A.
Abstract: ISBN: 0818654104, This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations.

38. Analog/digital testing of loaded boards without dedicated test points

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Vaucher, Ch., Balme, L., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Vaucher, Ch., and Balme, L.
Abstract: ISBN: 0780335414, This paper describes a new way to consider loaded board test fixturing, meeting the challenges of testing high density analog/digital loaded boards, such as mobile phones, camescopes, PCMCIA or fax boards. This method allows board area space savings of 7 to 15%.

39. Optimized synthesis of dedicated controllers with concurrent checking capabilities

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Leveugle, R., Saucier, G., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Leveugle, R., and Saucier, G.
Abstract: The authors present a novel synthesis method of dedicated controllers which aims at the detection of faults which cause errors in the state sequences. The state code flow is compacted through polynomial division. An implicit `justifying signature' method is applied at the state code level and ensures identical signatures before each join node of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison with reference data is greatly facilitated. This property is obtained by a clever state assignment, nearly without area overhead. The controllers can therefore be checked by signature analysis, either by a built-in monitor or by an external checker. The software implementation of the synthesis tool is presented, and the hardware implementation of the concurrent checking is described.

40. A new approach for early dependability evaluation based on formal property checking and controlled mutations

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Leveugle, R., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Leveugle, R.
Abstract: ISBN: 0769524060, The interest for early analyses of the functional impact of faults in a circuit is growing, due to the increasing probability of transient faults. However, experiments are often very long, especially when spatial and temporal multiplicity has to be taken into account in the fault model. Formal property checking is an appealing approach to perform comprehensive functional validations but is intended to validate properties only in nominal operation, not after a fault has occurred. This paper proposes a new approach combining formal property checking and the generation of specific circuit mutants to achieve efficient early identification of unacceptable effects of multiple faults.

41. Highly wireable multilevel synthesis with compiled cells

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Leveugle, R., Saucier, G., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG), Leveugle, R., and Saucier, G.
Abstract: ISBN: 0444873414, An original method for optimized multilevel synthesis of CMOS circuitry in terms of compiled cells is presented here. A compiled cell is the implementation on silicon of a `lexicographical' factorized Boolean expression. It is recalled how a compiled cell is obtained automatically from the Boolean expression. The rewriting of Boolean functions in terms of compiled cells is then addressed. This leads to a dense and regular layout by abutment of compiled cells. The wiring channels are so suppressed.

42. A fast algorithm for lapped nonorthogonal transform: application to the image Gabor transform

Author: France Telecom - CNET (CNET) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Poize, M., Renaudin, M., Venier, P., France Telecom - CNET (CNET) ; France Télécom, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Poize, M., Renaudin, M., and Venier, P.
Abstract: ISBN 0-8194-1018-7, A fast algorithm to solve the problem of the expansion of a one or two-dimensional finite and discrete signal into a lapped non-orthogonal time-modulated set of functions is described. Starting with current methods, such as Bastiaan's auxiliary functions and the ZAK transform, the authors describe a new algorithm resulting in a significant decrease in CPU time for image Gabor coefficients with only a slight approximation. The complexity of this algorithm is equivalent to the block Fourier transform plus two to four operations for each pixel. The global complexity is thus in O(M) compared with the most rapid current method in O(M logM). This algorithm is presented in the transform and the filtering formalism to show the interdependence of the two approaches. Theoretical results are demonstrated by an implementation study.

43. Netlist automatic extractor: 'An image processing based software for bare board test data generation'

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Benali, A., Balme, L., Vaucher, Ch., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Benali, A., Balme, L., and Vaucher, Ch.
Abstract: ISBN: 0818666900, Bare PCB (printed circuit board) test data generation softwares are based on vectorized calculations. When they fail, the automatic network list extractor software developed by IMD/TIMA succeeds thanks to image processing and pattern recognition on bitmaps.

44. Using concurrent and semi-concurrent on-line testing during HLS: an adaptable approach

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), LCIS-ESISAR ; Ecole Supérieure d'Ingénieurs en Systèmes Industriels Avancés Rhône-Alpes, Naal, M.A., Rakotoar, M., Simeu, E., Aktouf, C., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), LCIS-ESISAR ; Ecole Supérieure d'Ingénieurs en Systèmes Industriels Avancés Rhône-Alpes, Naal, M.A., Rakotoar, M., Simeu, E., and Aktouf, C.
Abstract: ISBN: 0769516416, This paper proposes a suitable on-line testing technique during the synthesis of complex electronic structures. Online testability is addressed by exploiting time redundancy in the scheduled data flow graph. On-line testability constraints are taken into account at the scheduling and allocation tasks. The technique implements non-concurrent; semi-concurrent or fully concurrent on-line tests according to the ability of the synthesized structure.

45. IP for embedded robustness

Author: iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Nicolaidis, M., iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Nicolaidis, M.
Abstract: ISBN: 0769514715, The following topics are dealt with: formal verification of designs; cooling layout; power analysis; SAT; BDD; interconnects; low power design; advanced mixed signal testing; collaborative design; logic synthesis; SoC; symbolic techniques; EDA tools; platform based design; analogue simulation; asynchronous circuits; BIST; network on chip; modelling; embedded systems; reconfigurable architectures; test resource partitioning; deep submicron design; logic synthesis; buffering; automatic design; object oriented systems; real time systems; online testing; fault tolerance; design space evaluation; architectural level synthesis; memory testing; high level synthesis; coupling and switching noise; and power optimisation.

46. Automatic generation algorithms, experiments and comparisons of self-checking PLA schemes using parity codes

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Boudjit, M., Nicolaidis, M., Torki, K., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Boudjit, M., Nicolaidis, M., and Torki, K.
Abstract: ISBN: 0818634103, Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is that they involve a significant increasing of the circuit area. Recent experiments on Berger-code encoded PLAs result on 46.9% average area overhead. In order to decrease this overhead, the authors present a tool that generates self-checking PLAs using parity encoding for the product terms and the outputs. This tool has been used for experimenting on several benchmark PLAs. In these experiments the authors retain for each PLA case the scheme involving the lower area overhead. Thus the mean overhead is reduced from 46.9% [TCR 91] to 37.2% (24.9% if a PLA named misex3 is not included).

47. A 120nm low power asynchronous ADC

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), ST Microelectronics (ST Microelectronics, Crolles) ; ST microelectronics, Allier, E., Renaudin, M., Sicard, G., Goulier, J., Dezzani, A., André, E., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), ST Microelectronics (ST Microelectronics, Crolles) ; ST microelectronics, Allier, E., Renaudin, M., Sicard, G., Goulier, J., Dezzani, A., and André, E.
Abstract: ISBN 1-59593-137-6, This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an Asynchronous Analog-to-Digital Converter (A-ADC) is tackled. Its principle is based on a non-uniform sampling scheme and asynchronous technology, that allow significant activity and power savings. A test chip targetting 10-bit speech applications has been fabricated using the 120nm CMOS process from STMicroelectronics. The power consumption is lower than 180µW leading to a Figure of Merit two times better than those of classical Nyquist converters recently published.

48. Checking signatures on boundary scan boards

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), DELET—UFRGS (DELET—UFRGS) ; DELET—UFRGS, iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Castro-Alves, V., Courtois, B., Lubaszewski, M., Nicolaidis, M., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), DELET—UFRGS (DELET—UFRGS) ; DELET—UFRGS, iROc Technologies (IROC TECHNOLOGIES) ; Cadence Connection - EDA Consortium - FSA - Cubic Micro, Castro-Alves, V., Courtois, B., Lubaszewski, M., and Nicolaidis, M.
Abstract: ISBN: 0818633603, Checking signatures on boundary scan boards

49. Using run-time reconfiguration for fault injection in hardware prototypes

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), ANTONI, L., Leveugle, R., Feher, B., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), ANTONI, L., Leveugle, R., and Feher, B.
Abstract: ISBN: 0769518311, In this paper, a new methodology for the injection of single event upsets (SEU) in memory elements is introduced. SEUs in memory elements can occur due to many reasons (e.g. particle hits, radiation) and at any time. It becomes therefore important to examine the behaviour of circuits when an SEU occurs in them. Reconfigurable hardware (especially FPGAs) was shown to be suitable to emulate the behaviour of a logic design and to realise fault injection. The proposed methodology for SEU injection exploits FPGAs and, contrarily to the most common fault injection techniques, realises the injection directly in the reconfigurable hardware, taking advantage of run-time reconfiguration capabilities of the device. In this case, no modification of the initial design description is needed to inject a fault, that results in avoiding hardware overheads and specific synthesis, place and route phases.

50. On balancing safety and reliability of hybrid and 'Bi-duplexed' systems

Author: Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), Courtois, B., Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG), and Courtois, B.
Abstract: Having defined the parameters necessary to the determination of a system, the author considers five systems (four hybrid systems with and without stop signal and a new redundancy scheme called Bi-duplexed redundant system) and the author compares these systems from both safety and reliability points of view, according to the complexity of the functional units. No hypothesis is made on the law of degradation of these functional units and of the additional circuits. However, this law must be the same for the two kinds of circuits.

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