Standard and ROM-based synthesis of FSMs with control flow checking capabilities

Authors :: CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG)
Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG)
Wending, X.
Rochet, R.
Leveugle, R.
CSI, INPG, Grenoble (CSI) ; Institut National Polytechnique de Grenoble (INPG)
Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) ; CNRS - Université Joseph Fourier - Grenoble I - Institut National Polytechnique de Grenoble (INPG)
Wending, X.
Rochet, R.
Leveugle, R.
Source :: Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043; Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043, Dec 1995, Princeton, NJ, United States. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.81-6, <10.1109/VTEST.1996.510839>
Abstract: ISBN: 0818673044<br />This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow.

Database :: OAIster
Journal :: Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043; Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043, Dec 1995, Princeton, NJ, United States. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.81-6, <10.1109/VTEST.1996.510839>
Notes :: Princeton, NJ, United States, Proceedings.-14th-IEEE-VLSI-Test-Symposium-Cat.-No.96TB100043, English
Publication Type :: Electronic Resource
Accession number :: edsoai.ocn892987485
Document Type :: Electronic Resource

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