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IP for embedded robustness
- Source :
- Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition; Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition, Dec 2001, Paris, France. IEEE Comput. Soc, Los Alamitos, CA, USA, pp.240-1, <10.1109/DATE.2002.998277>
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Abstract
- ISBN: 0769514715<br />The following topics are dealt with: formal verification of designs; cooling layout; power analysis; SAT; BDD; interconnects; low power design; advanced mixed signal testing; collaborative design; logic synthesis; SoC; symbolic techniques; EDA tools; platform based design; analogue simulation; asynchronous circuits; BIST; network on chip; modelling; embedded systems; reconfigurable architectures; test resource partitioning; deep submicron design; logic synthesis; buffering; automatic design; object oriented systems; real time systems; online testing; fault tolerance; design space evaluation; architectural level synthesis; memory testing; high level synthesis; coupling and switching noise; and power optimisation.
Details
- Database :
- OAIster
- Journal :
- Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition; Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition, Dec 2001, Paris, France. IEEE Comput. Soc, Los Alamitos, CA, USA, pp.240-1, <10.1109/DATE.2002.998277>
- Notes :
- Paris, France, Proceedings-2002-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition, English
- Publication Type :
- Electronic Resource
- Accession number :
- edsoai.ocn892987294
- Document Type :
- Electronic Resource