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A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

In this work, a phase noise reduction architecture for standalone oscillators is presented. The oscillator phase is divided and a voltage is generated by a type-I phase detector, which is compared with an ideal voltage to change the phase of the oscillator. Analysis shows that the loop parameters aid in phase noise suppression. The design is done in CMOS 90 nm technology for a 1 GHz ring oscillator. Post-layout simulations show that phase noise suppression is about 13 dB at 100 MHz offset for a division ratio of 2. [ABSTRACT FROM AUTHOR]

To measure the micro-displacement reliably with high precision, a single-ended eddy current sensor based on temperature compensation was studied in detail. At first, the principle of the eddy current sensor was introduced, and the manufacturing method of the probe was given. The overall design plan for the processing circuit was induced by analyzing the characteristics of the probe output signal. The variation in the probe output signal was converted to pulses with different widths, and then it was introduced to the digital phase discriminator along with a reference signal. The output from the digital phase discriminator was processed by a low-pass filter to obtain the DC component. At last, the signal was amplified and compensated to reduce the influence of temperature. The selection criteria of the frequency of the exciting signal and the design of the signal conditioning circuit were described in detail, as well as the design of the temperature-compensating circuit based on the digital potentiometer with an embedded temperature sensor. Finally, an experimental setup was constructed to test the sensor, and the results were given. The results show that nonlinearity exists in the single-ended eddy current sensor with a large range. When the range is 500 μm, the resolution can reach 46 nm, and the repeatability error is ±0.70% FR. Within the temperature range from +2 °C to +58 °C, the voltage fluctuation in the sensor is reduced to 44 mV after temperature compensation compared to the value of 586 mV before compensation. The proposed plan is verified to be feasible, and the measuring range, precision, and target material should be considered in real-world applications. [ABSTRACT FROM AUTHOR]

The Simons Observatory (SO) is a cosmic microwave background instrumentation suite being deployed in the Atacama Desert in northern Chile. The telescopes within SO use three types of dichroic transition-edge sensor (TES) detector arrays, with the 90 and 150 GHz Mid-Frequency (MF) arrays containing 65% of the approximately 68,000 detectors in the first phase of SO. All of the 26 required MF detector arrays have now been fabricated, packaged into detector modules, and tested in laboratory cryostats. Across all modules, we find an average operable detector yield of 84% and median saturation powers of (2.8, 8.0) pW with interquartile ranges of (1, 2) pW at (90, 150) GHz, respectively, falling within their targeted ranges. We measure TES normal resistances and superconducting transition temperatures on each detector wafer to be uniform within 3%, with overall central values of 7.5 m Ω and 165 mK, respectively. Results on time constants, optical efficiency, and noise performance are also presented and are consistent with achieving instrument sensitivity forecasts. [ABSTRACT FROM AUTHOR]

We demonstrate coherent optical frequency dissemination over a distance of 972 km by cascading two spans where the phase noise is passively compensated for. Instead of employing a phase discriminator and a phase locking loop in the conventional active phase control scheme, the passive phase noise cancellation is realized by feeding double-trip beat-note frequency to the driver of the acoustic optical modulator at the local site. This passive scheme exhibits fine robustness and reliability, making it suitable for long-distance and noisy fiber links. An optical regeneration station is used in the link for signal amplification and cascaded transmission. The phase noise cancellation and transfer instability of the 972-km link is investigated, and transfer instability of 1.1 × 10−19 at 104 s is achieved. This work provides a promising method for realizing optical frequency distribution over thousands of kilometers by using fiber links. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246. [ABSTRACT FROM AUTHOR]

This paper presents a low-power multi-rate clock and data recovery (CDR) for receivers of serial links. Its basic structure includes a current-mode logic bang–bang phase detector sampled by low-mismatch half-rate quadrature clocks, which are generated by voltage-controlled delay line (VCDL) and two-stage time-average circuits. The total delay of VCDL can be adjusted to accommodate a wide frequency range by its bias voltage, which is generated by a delay-locked-loop-based bias generator. The quadrature clocks are 64-phase adjustable with high linearity, which is realized by phase interpolator with a compensating structure. The parameters of phase detection loop are well designed to satisfy both high jitter tolerance and low clock jitter. Fabricated in a 40 nm CMOS technology, the CDR occupies an active area of 0.036 mm 2 only. With a wide operating range of 2–20 Gb/s, the chip consumes 62.5 mW, corresponding to an energy efficiency of 3.1 pJ/bit. The measured root-mean-square jitter and peak-to-peak jitter for the recovered clock at 9 GHz are 1.9 and 10.8 ps, respectively. [ABSTRACT FROM AUTHOR]

The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was 103.2μW demonstrating the effectiveness of 10T PFD over other conventional PFDs. [ABSTRACT FROM AUTHOR]

Abstarct: In this work, a new Charge Pump (CP) design including a Phase and Frequency Detector (PFD) is presented. The PFD is designed using the common topology of two D Flip Flops, AND gates and a controllable reset delay for the DFFs to compensate for process and tem-perature variations. The Charge Pump is using a bias cell which generates the necessary bias voltages, the clock driving cells which convert the single-ended UP and DOWN signals to differential and the core cell which comprises of six slices, each one contributing the same amount of current to the low pass filter. The output current is programmable with minimum and maximum values of 25 uA and 150 uA respectively. An extra option to double the output current is also added. A new technique has been adopted in terms of layout floorplan of the charge pump slices to eliminate the clock feedthrough mismatch between the differential UP and DOWN sig-nals. The technology used in this work is TSMC 65nm, while the supply voltage is 1 V. The main characteristics of the proposed design are modularity, low power, low noise, great linearity, small area, simplicity and performance. [ABSTRACT FROM AUTHOR]

A delay lock loop is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on a CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques with good current matching. The delay cell uses the bulk-driven technique and has less power consumption than the conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps. [ABSTRACT FROM AUTHOR]

An emerging challenge of integrated communication and sensing is the extraction of weak sensing signals transmitted through an unknown non-stationary channel. In this work, we propose a weak signal extraction method with weak measurement. Taking advantage of time division multiplexing, we preliminarily estimate the channel via adjustable finite impulse response filter, further suppressing the interfering signal caused by background noises via spectrum shift. By subsequently using the time-varying phase estimation method via weak measurement, the real-time detection of weak signals in the non-stationary channel is achieved. We demonstrate via theoretical analysis and confirmatory experiment that our method is able to amplify the phase shift, to suppress technical noise and to improve detection resolution limit, while proving robust against light source fluctuations, initial phase differences and detector saturation. The method hence enables weak sensing signal extraction with a low signal-to-noise ratio non-stationary channel. Furthermore, we interface our measurement method to squeezed light sources, offering the possibility of surpassing standard quantum limit. Integrated communication and sensing require high performance, sensing precision and preliminary knowledge of the channel, posing challenges to sensing weak signals from non-stationary channels. In this work, the authors demonstrate a weak signal extraction method with weak measurement, achieving weak signal sensing through a non-stationary channel. [ABSTRACT FROM AUTHOR]

The optical signal propagation used in satellite uplinks and downlinks is influenced by absorption, scattering, and changes in the atmospheric refractive index or turbulence, causing optical signal attenuation. A free space optics (FSO) communications system using coherent communication can improve the link sensitivity and reach higher distances. This article proposes a new architecture for the phase detector in an all-digital optical phase-locked loop (OPLL) for coherent optical detection. Firstly, the performance of the proposed phase detector is evaluated under Gaussian noise, where the best operation point is found for the OPLL working with two sample rates: 625 MSa/s and 10 GSa/s. The system analyses also take a non-negligible delay into account. Then, it will be evaluated and compared with an OPLL using an analog phase detector in the presence of atmospheric turbulence. Finally, in three different atmospheric turbulence conditions, the effect of wind speed on communication quality is investigated through the obtained bit error rate (BER) from the recovered data for a bit rate of 20 Gbps. The results show that the proposed digital phase detector can track a signal under longer feedback loop delays and fading signals. [ABSTRACT FROM AUTHOR]

A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flipflop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18 μm digital complementary metal–oxide– semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10-10 and 9.8×10-10, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ. [ABSTRACT FROM AUTHOR]

A single-phase/single-loop multiple-phase-shift-keying (m-PSK) demodulator is described. The demodulator relies on a linear range of an exclusive-OR (XOR) gate employed as a phase detector. The phase controller takes the average output from the XOR gate and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for an m-PSK signal. The proposed single-phase binary-/quadrature-PSK (BPSK/QPSK) demodulators have been implemented with low-cost discrete components. The core of the phase controller simply relies on number of stages of a full-wave rectifier and a linear amplifier built from well-known op-amp-based negative feedback circuits. The demodulator prototypes operate from a single supply of 5 V. At a carrier frequency of 100 kHz, both the BPSK and QPSK demodulators achieved the maximum symbol rate of 20 ksymbol/s respectively. At these symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 2×10-10 and 7×10-10. [ABSTRACT FROM AUTHOR]

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit ( F o M j i t t e r ) ~−236 dB. [ABSTRACT FROM AUTHOR]

An autocorrelation technique, which involves the correlation of a signal with its delayed version, could be used to demodulate the FM (Frequency Modulation) and PM (Phase Modulation) signals in a simple cost-effective manner. In this paper, an attempt has been made to understand the working principle of the autocorrelation technique for FM and PM demodulations. From the working principle, several design equations have been derived and these equations have been verified with the experimental results obtained from a 70 MHz autocorrelation-type FM receiver designed and developed indigenously. The demodulation of FM signal directly at RF (radio frequency) level has also been demonstrated using an autocorrelation-type C-band FM receiver at 4180 MHz. [ABSTRACT FROM AUTHOR]

Multi-h continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-h continuous phase modulation (CPM) is proposed based on a low-complexity decision-directed synchronization algorithm. Based on the maximum-likelihood estimation of the carrier phase and timing errors, we propose a reduced-complexity timing error detector with linear phase approximation (LPA) to the phase of the multi-h CPM. Compared with the traditional synchronization methods, it avoids derivative matched filtering and reduces about 2/3 of matched filters. The estimated accuracy and bit error rate (BER) performance of the LPA-based synchronization algorithm have no loss, as shown by the numerical simulation. Its stability is verified by the derived S-curve. Then, the receivers with the LPA-based synchronization for the three kinds of promising multi-h CPM are implemented on a Xilinx Kintex-7 FPGA platform. The experimental results show that the onboard tested BER of the proposed design has an ignorable loss in the numerical simulation. The implementation overhead on FPGA is significantly reduced by about 27% slices, 64% DSPs, and 70% block RAMs compared with the conventional method. [ABSTRACT FROM AUTHOR]

Infrared linear array detectors frequently experience vertical, low-frequency, and periodic stripe noise during imaging, stemming from electro-mechanical interference. Unlike conventional periodic disturbances, this interference showcases long periodicities and is uniquely columnar in orientation. Its presence, especially within the low-frequency domain, renders conventional filtering techniques ineffective and, at times, detrimental to image quality. Addressing this challenge, we introduce Fourier-Assisted Correlative Denoising (FACD), a correlation-centric denoising approach tailored for such unique interference patterns. This mechanism begins with the capture of a pure background image, inclusive of periodic noise, during the non-uniform correction phase of the infrared detector. Leveraging the noise's frequency domain attributes, we extract a one-dimensional single-cycle noise signal. The infrared image is subsequently segmented into parts, and using the detected noise periodicity, the one-dimensional signals for each segment are computed. By leveraging the correlation between these signals and the benchmark one-dimensional noise pattern, we ascertain the noise profile within each segment. This profile is then employed for spatial domain denoising across the entire image frame. Empirical assessments confirm that the FACD outperforms contemporary denoising techniques by augmenting the peak signal-to-noise ratio by approximately 2.5 dB, underscoring its superior robustness. Furthermore, in light of its specificity to this noise model, FACD rapidly denoises high-resolution real infrared linear array scans, thus meeting the stringent real-time and resolution imperatives of advanced infrared linear array scanning apparatuses. [ABSTRACT FROM AUTHOR]

The phase frequency detector (PFD) is an important component in a phase-locked loop (PLL). PFD detects the timing difference between the reference clock (REFCK) and the feedback clock (FBCK). PFD plays a major role in deciding the amount of time required by a PLL to achieve lock. The blind zone in the PFD causes inaccurate PFD output. This negatively impacts the PLL's lock-in time. The increase in lock-in time poses great challenges for developing high-speed PLLs. This paper proposes a PFD architecture that eliminates the reset pulse when the timing difference between the REFCK and the FBCK is significantly high. The elimination of the reset pulse in this way leads to a blind zone free PFD across process, voltage, and temperature (PVT) variations. The PFD is realized and implemented in the Cadence spectre environment using the UMC 0.18 μ m CMOS process. From the results, it can be stated that the designed PFD is blind zone free across PVT variations. The proposed PFD-based PLL locks faster than the traditional PFD-based PLL. The proposed PFD consumes 163 μ W power at a 100 MHz operating frequency which is the lowest compared to the earlier reported works. Its operational range is [ - 2 π , 2 π ]. The PFD occupies an area of 0.0069 mm 2 . The proposed design is well suited to low-power, high-speed PLL applications. [ABSTRACT FROM AUTHOR]

This paper presents formulations for time-based first-order and second-order high-pass, shelf, and notch filters. These formulations are an extension to the existing literature where low-pass filters are already developed using a multiphase controlled oscillator in conjunction with a phase detector and charge pump. The presented high-pass filter expands the circuit by introducing a current-controlled delay line (CCDL) that provides a direct path from input to output. By combining the high-pass filter with the low-pass filter, we show that shelf and notch filters can be obtained without an increase in circuit complexity compared to the high-pass filter. The results show good matching between the ideal small signal and the simulated time-based large signal frequency response. The simulated of total harmonic distortion for the filters shows an increase in distortion due to the nonlinearities introduced by the CCDL for the high-pass, notch, and shelf filter compared to the existing low-pass filter. The derivation of the new filter types allows the creation of complex high-order time-based filters by combining multiple first- or second-order filters. [ABSTRACT FROM AUTHOR]

In the current research work, an analysis of differential phase shift quantum key distribution using InGaAs/InP and Silicon-APD (avalanche photodiode) as single photon detectors is performed. Various performance parameters of interest such as shifted key rate, secure key rate, and secure communication distance obtained are investigated. In this optical fiber-based differential phase shift quantum key distribution, it is observed that Si-APD under frequency conversion method at telecommunication window outperforms the InGaAs/InP APD. [ABSTRACT FROM AUTHOR]

The effectiveness of the use of optical calibration in high-precision phase laser rangefinders has been evaluated. In order to ensure the specified accuracy of distance determination in order to establish the optimal frequency of distance measurement modes and optical calibration, an appropriate formula is recommended for estimating the switching frequency of signals at the input of the range finder measuring channel. It has been established that even when using optical calibration, the accuracy of distance measurement is affected by the error of the phase detector, which is part of the rangefinder. To minimize the influence of this error, a new method for the direct measurement of the phase shift in a range finder is proposed, as well as the use of a compensation method for measuring the phase shift. The corresponding block diagrams of rangefinders are considered, in which the proposed methods for measuring phase landslides are implemented, and analytical modeling of the processes that transform them is carried out. [ABSTRACT FROM AUTHOR]

We present a mathematical formalization and the results of computer simulation of an angular phase discriminator, which employs a linear antenna array with adaptation according to the Howells–Applebaum algorithm. A method of improving the direction-finding accuracy of the radio-emission sources, which provides the measurement unambiguity with a considerable increase in the measurement baseline, is proposed. The limiting values of the measurement baseline are determined with allowance for the unambiguity preservation in the case of an increase in the element number in the antenna array and a comparison of the slope of the direction-finding characteristics of the standard and proposed phase direction finders is performed with an admissible increase in the unambiguous-baseline sizes. [ABSTRACT FROM AUTHOR]

This study describes a non-contact low-cost X-band sensor system for determining the soluble solid content (SSC) of a sugar solution. The system adopts a transmission signal technique with two frequency pairs (10.2 GHz paired with 10.4 GHz and 10.2 GHz paired with 10.6 GHz) from three transceiver modules. Each module has a microstrip patch antenna, mixer circuit, and dielectric resonator oscillator. To simplify the transmission power frequency of each frequency pair, the frequency is down-converted to an intermediate frequency (IF) signal using a frequency mixer. The IF signals are then compared using a gain and phase detector to find their magnitude ratio and phase difference. The measured SSC-level data are randomly divided into three datasets and input to an artificial neural network (ANN) for training. The training output is the SSC level in Brix degree. The proposed ANN structure comprises four input nodes, eight hidden nodes, and four output nodes, affording low complexity and resource savings while providing 92.98% accuracy. Therefore, the proposed low-cost sensor system can achieve precise decision-making and real-time measurement. [ABSTRACT FROM AUTHOR]

Within the framework of the development of the theory of hidden oscillations, the problem of determining the boundary of global stability and revealing its hidden parts corresponding to the nonlocal birth of hidden oscillations is considered. For a phase-locked loop with a proportional-integrating filter and a piecewise-linear phase detector characteristic, effective methods for determining bifurcations of global stability loss, for obtaining analytical formulas for bifurcation values, and for constructing trivial and hidden parts of the global stability boundary are suggested. [ABSTRACT FROM AUTHOR]

Due to reset process of phase frequency detector (PFD), the induced blind zone degrades the acquisition performance of phase-locked loop. Most of reported blind-zone free solutions are based on transistors, which cannot be implemented with field programmable gate array (FPGA). Therefore, a blind zone-suppressed PFD suit for FPGA is proposed in this paper. If any trigger condition of blind zone is met, the proposed reset mask or edge recovery operation is active. Thereafter, the corresponding edge of detected clock is kept or recovered to alleviate the effect of blind zone. At last, the proposed PFD is written by Verilog hardware description language, and implemented with Xilinx Virtex-7 XC7VX330TFFV1157-3. The occupied resources are 9 LUTs and 15 FFs, and the logic delay of critical path is only 0.264ns. The correctness of blind zone-suppressed PFD is also verified by simulation results. [ABSTRACT FROM AUTHOR]

In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 M H z − 4 G H z operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 p s in the phase characteristics which improves the output phase noise as −132.9 d B c / H z at 1 M H z offset frequency. The power consumption is minimised upto 417.3 μ W @ 4 G H z operating frequency. The design is simulated in standard 0.18 \mum CMOS technology node with 1.8 V power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication. [ABSTRACT FROM AUTHOR]

Despite extensive investigations on the mechanism of laser-irradiated solid propellants, formulating an accurate model that characterizes more details of laser-target interactions remains a challenging task. In this paper, a thermal model for nanosecond pulsed laser ablation of aluminum was developed using the finite volume method which considers the instant recession on the propellant surface and the non-Fourier effect during heat conduction. The robust coupling iteration scheme adopted in the model tracks the dynamic boundary condition due to instant propellant removal. In particular, the pre-qualified threshold is used as discriminator for phase explosion and the thermal relaxation time is introduced to quantify the non-Fourier effect on heat conduction. In addition, the temperature-dependent physical and optical parameters of the propellant were also regarded in the proposed model. The numerical implementations for Gaussian laser ablation of aluminum were performed at different laser fluences and thermal relaxation times. The theoretical computation of the ablation depth coincides well with the experimental results to validate the feasibility of the model. • The thermal interaction of an ultra-short pulsed laser with metal was investigated. • The material moving front during heat transfer was modeled using finite volume method. • A modified critical threshold was used as a discriminator for metal phase explosion. • The thermal relaxation time was introduced to quantify the non-Fourier effect. [ABSTRACT FROM AUTHOR]

Robust and reliable multi-modal image matching is an essential and challenging technique in the multi-modality involved scenarios for image fusion, image mosaic, and visual navigation. Existing image matching methods cannot simultaneously solve the scale and rotation distortion caused by different viewpoints and the nonlinear radiation distortion caused by different imaging environments or mechanisms. To address these problems, a multiscale structural feature transform method is proposed for multi-modal image matching, which consists of three blocks: multiscale structural feature detector, symmetric log-polar descriptor, and point matching with position correction. The multiscale structural feature detector constructs the phase congruency map based Difference of Gaussian image pyramid for the scale-invariant feature points detection to tackle the nonlinear radiation distortion. The feature points are detected within 10-neighborhood instead of 26-neighborhood to produce sufficient points on the phase congruency map with very sparse texture. The symmetric log-polar descriptor utilizes the multiscale structure principal direction and symmetric bins to improve the robustness of the descriptor to rotation and nonlinear radiation distortion. At last, the point matching with position correction corrects the position of feature points to compensate the position offset between different images caused by the scale and rotation distortion and the nonlinear radiation distortion, which increases the number of correct matches and improves the transformation consistency between matched points. In the experiment, the proposed method in this paper is compared with seven state-of-the-art methods. Experimental results verify the superiority of the proposed method and its robustness to the scale and rotation distortion and the nonlinear radiation distortion. In addition, we demonstrate the effectiveness of the proposed three blocks by the ablation experiments. • A multiscale structural feature transform is proposed for multi-modal image matching. • The multiscale structural feature detector extracts repeatable and salient points. • The symmetric log-polar descriptor achieves rotation-invariance and robustness. • The offsets of feature points are corrected to produce more correct match pairs. [ABSTRACT FROM AUTHOR]

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ( V DD , w p , and w n ) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters V DD , w p , and w n are likewise determined using this procedure to maximize the circuit's overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180 nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are − 1 5 9. 5 6 dBc/Hz, 9.83 μ W, and 10.21 GHz, respectively, and it occupies a chip area of 300.41 μ m 2 . The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 μ s. [ABSTRACT FROM AUTHOR]

GPS receivers have a wide range of applications, but are not always secure. A spoofing attack is one source of conscious errors in which the counterfeit signal overcomes the authentic GPS signal and takes control of the receiver's operation. Recently, GPS spoofing attack detection based on computational algorithms, such as machine learning, classification, wavelet transform and clustering, has been developing. This paper proposes multiple clustering algorithms for accurately clustering the authentic and spoofing signals, called subtractive, FCM and DBSCAN clustering. The spoofing attack is recognized using two distinct features: moving phase detector variance and norms of correlators. Spoofing and authentic signals have different patterns in the proposed features. According to the Dunn and Silhouette indexes, the validation of the results is investigated. The Dunn values for the proposed approaches are 0.8592, 0.5285 and 0.6039 for DBSCAN, FCM and subtractive clustering, respectively. Also, the DBSCAN algorithm is implemented at the RTL level because of its highest value for the Dunn index and algorithm verifiability. Using the Vivado tools, this algorithm is implemented and designed on a Xilinx Virtex 7 xc7vx690tffg1930-3 hardware device for two-dimensional data with 32-bit accuracy and 130 data points. [ABSTRACT FROM AUTHOR]

Synchronous reference frame-phase lock loop (SRF-PLL) is most widely used for grid synchronization applications. PLL structure typically consists of a phase detector (PD), loop filter (LF) and voltage control oscillator (VCO). Design and tuning of proportional-integral (PI) controller based LF is a changeling task under distorted grid voltage conditions. Conventional tuning methods such as symmetrical optimum (SO) and Ziegler-Nichols techniques are used to tune the PI controller, resulting in increased phase margin (PM) of the system. However, high bandwidth develops harmonics in the extracted signals under non-ideal grid conditions and affects the stability. In this research article, a new optimum setting algorithm is proposed to tune the PI controller and effective synchronization is achieved. The plant is reduced as a first-order plus dead time delay (FOPDT) model and critical gain; critical frequency of the open loop system transfer function is used to model the LF of the SRF PLL system. The controller parameters are derived such that minimization of time-weighted integral performance criteria is achieved and phase angle, frequency of the grid voltage is accurately extracted. The performance of the proposed optimum setting algorithm for the SRF-PLL grid synchronization technique is discussed in detail and simulation results are presented. [ABSTRACT FROM AUTHOR]

A low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption. [ABSTRACT FROM AUTHOR]

This paper addresses a key limitation of using existing detection and controller data of signalized intersections to build performance metrics in the automated traffic signal performance measures (ATSPMs) platform. Many intersections were installed with lane-by-lane stopbar detectors for actuated and adaptive signal controllers. Stopbar detector actuations are valuable inputs for signal controllers and intersection performance but are not the ideal advanced detector inputs for several key ATSPM metrics such as arrival on red (AoR) and Purdue coordination diagram (PCD). This paper presents a vehicle trajectory reconstruction algorithm based on shockwave theory to estimate advanced vehicle detections from stopbar arrivals and departures. Model parameters including shockwave speeds, free-flow velocity, acceleration, and deceleration rates were directly measured using spatial-temporal maps (STMaps) generated from roadside closed-circuit television (CCTV) camera video. The initially measured parameters were optimized using the genetic algorithm (GA) that was subsequently validated quantitively and qualitatively. Finally, combining the stopbar detector and signal phase and timing, a new coordination diagram was designed to enable traffic operators to identify mobility patterns and safety-critical events quickly. This research sought to utilize existing data sources to meet performance metric requirements while avoiding intensive investment to upgrade the current infrastructure. The STMap-based method substantially reduces the complexity of obtaining necessary model parameters. The new stopbar-based Rutgers coordination diagram enriches the visualization tools for intersection performance measures from controller and detection systems. [ABSTRACT FROM AUTHOR]

Background: Chest X-ray (CXR) images are commonly used to show the internal structure of the human body without invasive intervention. The quality of CXR is an important factor as it affects the accuracy of a clinical diagnosis. Unfortunately, it is difficult to always get good quality CXR scans due to noises and scatters. Purpose: Recently, wavelet directional CycleGAN (WavCycleGAN) has shown promising results in image restoration tasks by removing noise and artifacts without sacrificing high-frequency components of the input image. Unfortunately, WavCycleGAN directly reconstructs wavelet directional images that require a wavelet transform in both the training and test phases, resulting in additional processing steps and unnatural artifacts originating from the wavelet domain image.In addition,WavCycleGAN can only process artifact-related subbands, so it is difficult to apply WavCycleGAN when different levels of artifacts are present in all subbands. To address this, here we present a novel unsupervised CXR image restoration scheme with similar or even better artifact removal performance than WavCycleGAN in spite of wavelet transform being only applied in the training phase. Methods: We introduce a novel wavelet subband discriminator which can be combined with CycleGAN or switchable CycleGAN, where wavelet transform is applied only in the training phase for discriminators to match the distribution of wavelet subband components. In our framework, the image restoration network can be still applied in the image domain to prevent unnatural artifacts of the wavelet domain image with the help of the image-domain cycle-consistency loss. In addition, using wavelet subband discriminator makes it possible to remove artifacts in all subbands by utilizing frequency-specific wavelet subband discriminators. Results: Through extensive experiments for noise and scatter removal in CXRs, we confirm that our method provides competitive performance compared to existing approaches without additional processing steps in the test phase. Furthermore, we show that our wavelet subband discriminator combined with the switchable CycleGAN can provide the flexibility by generating different levels of artifact removal. Conclusions: The proposed wavelet subband discriminator can be combined with the existing CycleGAN or switchable CycleGAN structures to construct an efficient unsupervised CXR image reconstruction. The advantage of our wavelet subband discriminator-based CXR image restoration is that, unlike traditional WavCycleGAN, it does not require any additional processing steps in the testing phase and does not generate unnatural artifacts originating from the wavelet domain image. We believe that our wavelet subband discriminator can be applied to various CXR image applications. [ABSTRACT FROM AUTHOR]

Multiple object detection and tracking play a very crucial role in solving several elementary problems in real-time surveillance video analysis and computer vision. However, it is a challenging problem because real-time surveillance videos are typically affected by a variety of adverse environmental effects. In this work, we propose a novel surveillance framework, called a unifocal motion tracking surveillance system (UMTSS), for multi-object tracking in real-time videos. The proposed UMTSS combines two significant steps. First, a Faster-RCNN with inception-v2 model is employed here to detect multi-objects efficiently in each video frame. Then, a unifocal feature-based KLT (Kanade-Lucas-Tomasi) method is proposed for tracking objects across the video frames based on region proposals generated by the object detector in the previous phase. Also, we have proposed a new tracking parameter, called dynamic tracking accuracy (DTA), to quantify the performance of the tracking algorithms. The performance of our UMTSS has been evaluated on five standard crowd video databases, namely CrowdHuman, PETS, UCSD, AGORASET and CRCV, and compared with state-of-the-art methods in terms of different qualitative and quantitative measures. It has been observed that our UMTSS outperforms the state-of-the-art methods. [ABSTRACT FROM AUTHOR]

The quantum critical detector (QCD), recently introduced for weak signal amplification [L.-P. Yang and Z. Jacob, Opt. Express 27, 10482 (2019)], functions by exploiting high sensitivity near the phase transition point of first-order quantum phase transitions (QPTs). We contrast the behavior of the first-order and the second-order quantum phase transitions in the detector. We find that the giant sensitivity, which can be utilized for quantum amplification, only exists in the first-order QPTs. We define two new magnetic order parameters to quantitatively characterize the first-order QPT of the interacting spins in the detector. We also introduce the Husimi Q -functions as a powerful tool to show the fundamental change in the ground-state wave function of the detector during the QPTs, especially the intrinsic dynamical change within the detector during a quantum critical amplification. We explicitly show the high figures of merit of the QCD via the quantum gain and the signal-to-quantum noise ratio. Specifically, we predict the existence of a universal first-order QPT in the interacting-spin system resulting from two competing ferromagnetic orders. Our results motivate new designs of weak signal detectors by engineering first-order QPTs, which are of fundamental significance in the search for new particles, quantum metrology, and information science. [ABSTRACT FROM AUTHOR]

In this article, a half-tangent phase-locked loop (HTan-PLL) is proposed for variable-frequency grids of more electric aircrafts. First, the pros and cons of the synchronous reference frame PLL (SRF-PLL) are discussed in a nonlinear framework. To address the disadvantages, a half-tangent phase detector (PD) is developed and a novel PLL is then proposed. Subsequently, a phase portrait-based analysis and a Lyapunov function-based argument are provided. It is proven that the HTan-PLL has a good performance in terms of steady-state accuracy and fast dynamics, even under large frequency changes. Compared with the conventional SRF-PLL, the proposed HTan-PLL outperforms with the following features: faster dynamics than the SRF-PLL when the frequency varies largely; no unstable equilibrium points, while the SRF-PLL has infinite unstable equilibrium points; and when the grid frequency jumps widely, the HTan-PLL converges to the unique equilibrium point (0,0). By contrast, the SRF-PLL goes to different equilibrium points. Experimental tests are provided, which verify the superior performance of the HTan-PLL. [ABSTRACT FROM AUTHOR]

In phase frequency detector (PFD) phase characteristics, the presence of dead zone fails to turn on the charge pump (CP) of the phase locked loop (PLL). This degrades the phase noise in PLL. To overcome this drawback in PFD, a circuit to eliminate dead zone using pass transistor logic (PTL) and delay cells (DCs) is proposed in this paper. The proposed circuit has been implemented in UMC 0.18 μ m CMOS process and simulated in a cadence spectre environment. From the post layout simulation results, it is noted that for a phase difference of - π to + π , the PFD achieves 100% linearity and is free from the dead zone. The designed PFD consumes power of 28.8 μ W at an operating frequency of 100 MHz. The proposed PFD is also verified across process voltage temperature (PVT) variations for its linearity. The PFD is independent of duty cycle variations of its input clock signals. It occupies an area of 312.4 μ m 2 . [ABSTRACT FROM AUTHOR]

This paper presents an LO phase shifter with frequency tripling for 28-GHz 5G transceivers. The phase shifting and frequency tripling are achieved using an injection-locked oscillator and injection-locked frequency tripler, respectively. A phase detector based on third harmonic mixing is also implemented and is used to detect the applied phase shift, supporting automatic calibration of the phase shifter. Additionally, an algorithm to automatically tune the oscillators to their respective locking frequency is presented. To test the phase shifter, a 24–30-GHz sliding-IF receiver is implemented. Simulations show that a > 360 ∘ tuning range over the full 24–30 GHz span is achieved, with a gain variation of 0.11 dB or less, and that the phase detector has an rms phase error of < 2.5 ∘ . The circuit is implemented in a 28nm FD-SOI CMOS process and the entire chip measures 1080 μ m × 1080 μ m , including pads, and consumes 27–29 mW from a 1 V supply. [ABSTRACT FROM AUTHOR]

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage‐controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase‐frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage‐controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed‐forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide‐by‐47 and divide‐by‐48) that lacks a few extra flip‐flops which save considerable power and improves the frequency difficulties of the multi‐band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1‐μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS‐based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability. [ABSTRACT FROM AUTHOR]

The paper discusses a multichannel monitoring device with a speed-optimal phase-locked loop system, which, by performing simultaneous measurements of several clock signals against the reference one, processing and transmitting measurement results by an IP-network in real time, increases the accuracy and precision of providing time synchronization signals for SMART Grid energy system. Analytical expressions where established to determine the conditions under which in the optimal system of phase-locked loop has no influence on the transient process of limiting the periodic static characteristic of the phase discriminator. Experimental studies have confirmed meeting the norms of the European standard ETS 300 462-4 for the time parameters of the reference signal generated by the phase-locked loop system, which is optimal in terms of speed, and also demonstrated the effectiveness of the proposed implementation of the device for multi-channel monitoring of time synchronization signals for SMART Grid of power systems. [ABSTRACT FROM AUTHOR]

This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoMT is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature. [ABSTRACT FROM AUTHOR]

The phase frequency detector/charge pump is a significant source to raise the in-band phase noise of the phase-locked loop (PLL). The proposed CMOS-based pass transistor phase frequency detector (PT-PFD) solves the cycle skipping issue by improving the blind zone which in turn improves the phase noise performance. At the same time, in order to further improve the performance of the PLL, charge pump is integrated with the proposed design. In this case, the reset time has been reduced and thus the proposed PFD/CP functions up to the frequency of 1.5 MHz – 4.2 GHz. In addition, the modified pass transistor PFD architecture contains an advantage of less number of transistor count which consumes low power, i.e., 317.37 μ W . The design is based on standard 0.18 μ m CMOS process technology with the supply voltage of 1.8 V. Moreover, the proposed design has completely eliminated the dead zone, and blind zone is minimized up to 44.23 ps which improves the phase noise to −133.8 dBc/Hz at 1 MHz offset frequency. The PFD/CP proposed herein just requires lower power consumption while producing less noise in charge pump phase-locked loop (CPLL) application. [ABSTRACT FROM AUTHOR]

Sensorless drives of interior permanent magnet synchronous motors (IPMSMs) find a broad range of applications due to their inherent benefits. In practical electrified propulsions, the IPMSM drives are usually working in highly utilized conditions where the performance and stability could deteriorate. Without considerable compensation, this vulnerability causes the existing phase-locked loops (PLLs), estimators, or observers to lose the synchronization with the rotor position. To achieve better performance and reduce the estimation error, in a PLL-type framework for sensorless control, a position error observer (PEO) utilizing the current errors as correction terms plays the role of the phase detector. A reduced-order extended state observer (ESO) is presented to form the loop filter with a switched nonsmooth feedback structure. The outstanding property of the PEO and nonsmooth ESO is verified through experiments. The results demonstrate its strong adaptability for model uncertainties and disturbances along with the quick convergence speed and minimal oscillation. [ABSTRACT FROM AUTHOR]