Back to Search
Start Over
A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator.
- Source :
- International Journal of Electrical & Computer Engineering (2088-8708); Dec2023, Vol. 13 Issue 6, p6102-6117, 16p
- Publication Year :
- 2023
-
Abstract
- A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flipflop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18 μm digital complementary metal–oxide– semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10<superscript>-10</superscript> and 9.8×10<superscript>-10</superscript>, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 20888708
- Volume :
- 13
- Issue :
- 6
- Database :
- Complementary Index
- Journal :
- International Journal of Electrical & Computer Engineering (2088-8708)
- Publication Type :
- Academic Journal
- Accession number :
- 173717468
- Full Text :
- https://doi.org/10.11591/ijece.v13i6.pp6102-6117