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A 5.91–8.94GHz phase‐locked loop in 65 nm CMOS for 5G applications.
- Source :
-
Microwave & Optical Technology Letters . Apr2023, Vol. 65 Issue 4, p975-980. 6p. - Publication Year :
- 2023
-
Abstract
- A low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 08952477
- Volume :
- 65
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- Microwave & Optical Technology Letters
- Publication Type :
- Academic Journal
- Accession number :
- 162399026
- Full Text :
- https://doi.org/10.1002/mop.33368