A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector.

A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply. [ABSTRACT FROM AUTHOR]