FPGA Design of Blind Zone-Suppressed Phase Frequency Detector via Reset Mask and Edge Recovery Operations.

Due to reset process of phase frequency detector (PFD), the induced blind zone degrades the acquisition performance of phase-locked loop. Most of reported blind-zone free solutions are based on transistors, which cannot be implemented with field programmable gate array (FPGA). Therefore, a blind zone-suppressed PFD suit for FPGA is proposed in this paper. If any trigger condition of blind zone is met, the proposed reset mask or edge recovery operation is active. Thereafter, the corresponding edge of detected clock is kept or recovered to alleviate the effect of blind zone. At last, the proposed PFD is written by Verilog hardware description language, and implemented with Xilinx Virtex-7 XC7VX330TFFV1157-3. The occupied resources are 9 LUTs and 15 FFs, and the logic delay of critical path is only 0.264ns. The correctness of blind zone-suppressed PFD is also verified by simulation results. [ABSTRACT FROM AUTHOR]