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Abstract Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (V hold) applied to the programmed device. When the V hold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.

Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation. [ABSTRACT FROM AUTHOR]

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology. [ABSTRACT FROM AUTHOR]

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.

As the high-voltage (HV) and low-voltage (LV) circuits are integrated together in a common silicon substrate, the parasitic latch-up path between neighboring HV and LV circuits with limited spacing in layout would be triggered into latch-up state to cause unrecoverable failure in the chip. In this work, the isolation ring of HV n-well (HVNW) / N-buried layer (NBL) with Schottky-embedded junction to overcome the lateral HV-to-LV latch-up path was proposed and verified in a $0.18{\mu }\text{m}$ HV bipolar-CMOS-DMOS (BCD) technology. From the experiment results of the proposed Schottky-embedded isolation ring, the holding voltage (Vh) in the lateral HV-to-LV parasitic latch-up path can be increased to be greater than the voltage difference between the different power supplies of the neighboring HV and LV circuits. Furthermore, the layout spacing between the neighboring HV and LV circuits can be significantly reduced to save chip area. The proposed Schottky-embedded isolation ring is a cost-effective solution to provide good latch-up immunity among the HV-to-LV circuit blocks with a short layout distance.

In this paper, a series of Low Voltage Triggering Silicon-Controlled Rectifier (LVTSCR)-based devices were designed and fabricated in a 0.25 μm Bipolar-CMOS-DMOS (BCD) process. Two distinct methods, the integration of additional doping regions and current paths, are investigated to improve the proposed devices' holding voltage (V h). Two-dimensional device simulation is employed to elucidate the working mechanism of these ESD protection devices, complemented by the introduction of a transmission line pulse (TLP) measuring system to assess their ESD protection capabilities. Comparative analysis of TLP results reveals that both methods contribute significantly to the augmentation of holding voltage in LVTSCR ESD protection devices. The refined structure, LVTSCR_BN, with two additional current paths, surface and buried, demonstrated a noticeable increment in holding voltage. With its holding voltage of 7.619 V and trigger voltage of 10.61 V, LVTSCR_BN is proved suitable for the ESD protection of circuits operating at the voltage of 5 V. [ABSTRACT FROM AUTHOR]

Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/ μ m without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations. • A MOS shunt LVTSCR has excellent holding voltage for 3.3V application. • The effect of current shunt on holding voltage is studied in detail. • The design principle of the current-shunt device is presented. [ABSTRACT FROM AUTHOR]

As the characteristic size of semiconductor devices in ICs decreases, ICs are becoming more sensitive to electrostatic discharge (ESD). Electrostatic protection has become one of the most important reliability indexes in ICs, and the ESD protection structure has also become a difficult problem in chip design. A sensor exposed to static electricity can be damaged and its output signal can be disturbed. Therefore, electrostatic protection also plays an important role in sensors. As the scale of ICs increases, the number of chip pins is increasing and a larger area is being used for ESD protection circuits, resulting in higher costs. Silicon controlled rectifier (SCR) ESD protection devices have the highest performance per unit area among the known ESD protection structures, and are thus the first choice for low-cost, on-chip ESD design solutions. In this study, through a Sentaurus simulation, two SCRs with different structures (a directly connected SCR and a modified lateral SCR) are established, and transmission line pulse tests are carried out on the two devices. The key characteristic indexes are analyzed theoretically and by using experimental data. According to the simulation results, the opening voltage of the directly connected SCR is about 1.5 V and its secondary breakdown current is above 5 A, indicating that the device has a high protection level. [ABSTRACT FROM AUTHOR]

4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

For robust high-voltage (HV) electrostatic discharge (ESD) protection engineering, such as 8-KV or 15-KV ESD target, the silicon-controlled rectifiers (SCRs) with high holding voltage are needed to mitigate latch-up risk. However, when implemented in the multifinger layout configuration for satisfying high robust ESD requirement, these devices may encounter holding voltage deterioration problems. In this article, such holding voltage deterioration has been explored by theoretical analysis and experimental verification. The transmission line pulsing (TLP) results indicate that the sharing of adjacent WELL pickup and removing of inner guard ring in the typical multifinger layout (TMF) are the root causes for holding voltage deterioration. Through the appropriate test-key design, both of these culprits have been identified independently. Finally, by keeping the average WELL pickup length and average number of parasitic paths of each SCR finger in the multifinger layout constant, such holding voltage deterioration can be restrained effectively, achieving a stable holding voltage regardless of the number of fingers. Therefore, this article offers very useful work for HV ESD engineering. [ABSTRACT FROM AUTHOR]

The negative holding voltage of high-voltage (HV) dual-directional silicon-controlled rectifier (DDSCR) is usually attenuated to a very low level due to the grounded guard ring, which has been ignored by many researchers nowadays. In this brief, a novel symmetrical DDSCR (SDDSCR) is proposed to suppress the deterioration of DDSCR’s negative holding voltage. By introducing a diffusion resistor into the p-type guard ring (PGR), experimental results indicated that the reverse parasitic SCR path associated with PGR is suppressed effectively. Thus, a symmetric high holding voltage characteristic is implemented for SDDSCR without increasing any silicon footprint. Moreover, the PGR resistor technology presented in this brief can be extended to various existing HV DDSCRs, which could improve their negative holding voltage deteriorated by guard ring. [ABSTRACT FROM AUTHOR]

The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-voltage and high-voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low holding voltage of existing DDSCRs is not suitable for high-voltage applications. In this study, a novel DDSCR with a high holding voltage and low dynamic resistance is proposed and its electrical characteristics are verified. The proposed DDSCR has two additional internal parasitic bipolar transistors compared to a conventional low-triggering voltage DDSCR (LTDDSCR). Self-gate biasing reduces latch-mode feedback between the parasitic bipolar transistors in the SCR. The device is fabricated using 0.13 um BCD processes and implements a segment layout resulting in a very low dynamic resistance of 2.2 Ω and excellent holding voltages of up to 17.2 V. The proposed DDSCR demonstrates improved reliability and area efficiency for 12 V applications.

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications. [ABSTRACT FROM AUTHOR]

Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology reveal the persisting reliability threat single-event latchup (SEL) poses to advanced technology nodes. SEL is characterized over a wide range of supply voltages and temperatures for this technology node. SEL data is analyzed to determine the holding voltage ($V_{\mathrm {HOLD}}$) required to sustain SEL, which can be as low as 0.85 V at elevated temperatures. Such low SEL holding voltage within 100 mV of nominal supply voltage poses a major reliability threat. [ABSTRACT FROM AUTHOR]

This article investigates the effect of N-type buried layer (NBL) on the holding voltage and failure current of conventional low voltage triggered silicon-controlled rectifier (LVTSCR) and conventional dual directional silicon-controlled rectifier (DDSCR) devices. LVTSCR and DDSCR with N-type buried layer are fabricated on a 0.18- $\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. In order to verify and predict the effect of N-type buried layer on the characteristics of ESD protection devices, a transmission line pulse (TLP) testing system and a 2-dimension device simulation platform have been used in this work. According to the measurement results, the holding voltage (${\mathrm{ V}}_{\mathrm{ h}}$) and failure current (${\mathrm{ I}}_{\mathrm{ t2}}$) of the LVTSCR and DDSCR can be drastically improved by adding N-type buried layer. [ABSTRACT FROM AUTHOR]

This article proposes a dual-directional silicon-controlled rectifier (SCR) with a novel structure and high holding voltage to improve the electrostatic discharge (ESD) design area efficiency in high-voltage environments. In terms of structure, by decreasing the emitter injection efficiency of the p-n-p parasitic bipolar transistor formed at the bottom of the gate region, the SCR positive feedback gain is reduced, which endows the proposed device with improved snapback characteristics compared with the conventional low-voltage triggering SCR (LVTSCR) and low-trigger dual directional SCR (LTDDSCR). This article conducted 2-D and mixed-mode simulations to compare and analyze the operating principles of the proposed and traditional devices. Additionally, experimental devices were fabricated under the same conditions using the 0.13-μm process to verify their electrical properties and latch-up immunity by measuring the transmission line pulse (TLP) and transient latch-up (TLU). This article also conducted a detailed analysis on the optimization of electrical properties for the ESD design window of the proposed device according to the design variables and application of segment topology, and also analyzed the temperature reliability using a hot chuck control system. The measurement results reveal that the proposed device is highly suitable for the 12-V-class ESD design window, has improved reliability, and can provide excellent area efficiency in related applications. [ABSTRACT FROM AUTHOR]

In this letter, a new silicon-controlled rectifier (SCR) structure fabricated using 4H-SiC materials has been proposed and investigated. The proposed structure alleviates the strong-snapback phenomenon that occurs in the 4H-SiC SCR and demonstrates low trigger voltage and high holding voltage characteristics. The proposed device exhibits improved snapback characteristics with very high holding voltage against electrostatic discharge surges owing to the structural features and application of segment topology. It also has excellent on-resistance and improved thermal reliability owing to the physical characteristics of 4H-SiC. Traditional SCR and low-voltage trigger SCR (LVTSCR) are fabricated with 4H-SiC under the same conditions and their electrical characteristics are comparatively analyzed with those of the proposed SCR. This study also evaluates the electrical characteristics at high temperatures (300–500 K) to verify the high- temperature reliability of the proposed structure. [ABSTRACT FROM AUTHOR]

This article concerns experimental and simulation results on nonstable latchups (SLs) in CMOS integrated circuits (ICs) under pulsed laser irradiation. Different transient responses in elements of the p-n-p-n structure and irregular ionization distribution on the IC surface are the main reasons for non-SLs. Radiation experimental test results are presented as well as a discussion of non-SL mechanisms. [ABSTRACT FROM AUTHOR]

This article proposes a new silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection device suitable for 5-V applications. The proposed ESD protection device has an additional n-p-n parasitic bipolar transistor that provides an extremely short ESD discharge path. Compared with the conventional Low-Voltage-Trigger SCR (LVTSCR) and Low-Ron SCR (LRSCR), it has excellent ON-resistance and improved reverse characteristics. Furthermore, it has structurally enhanced trigger voltage and holding voltage characteristics. A conventional LVTSCR, LRSCR, and the proposed ESD protection device were fabricated with the same width using a 0.18-μ bipolar CMOS DMOS (BCD) process to verify the improvement in electrical characteristics and current driving capability of the new device. Transmission line pulsing (TLP) and a hot chuck control system were used to measure and compare the latch-up, electrical characteristics, and temperature reliability of the three devices. The measurements demonstrate that the proposed ESD protection device provides improved reliability and higher area efficiency for 5 V or similar applications. [ABSTRACT FROM AUTHOR]

This paper proposes a new structure of silicon controlled rectifier (SCR)-based ESD protection circuit using a penta-well for ESD protection in 5 V applications. The proposed circuit exhibits higher holding voltage and current-driving capability than low Ron SCR (LRSCR) ESD protection circuits. The existing LRSCR ESD protection circuit and the proposed ESD protection circuit were fabricated using the 0.18 μm BCD process. The electrical and latch-up characteristics were compared and analyzed using transmission line pulse measurement and a transient-induced latch-up test.

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (Vt) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (Vh) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the Vt of the proposed circuit increased from 14 V to 27.8 V, and Vh increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V.

The diode-triggered silicon-controlled rectifier (DTSCR) is an important device for the electrostatic discharge (ESD) protection of low-voltage integrated circuits, and its trigger voltage is determined by the forward turn-on voltage of diode string and the voltage drops on the parasitic resistors of metal interconnects. For the conventional DTSCR, the voltage drops on the parasitic resistors are often negligible so its triggering voltage is mainly determined by the forward turn-on voltage of diode string, which decreases with increasing temperature due to the inherited negative temperature coefficient. In this paper, an improved and novel device called thermal-stable DTSCR (TSDTSCR) is proposed to offer an improved ESD protection stability at elevated temperatures. This is done by changing and optimizing the 3-D layout. In particular, the experimental results show that the trigger voltage drop of the TSDTSCR can be reduced to 13.5% at 125 °C, comparing to 27.18% of the DTSCR. The holding voltage of the TSDTSCR is also more stable than that of the DTSCR over a wide range of temperatures. [ABSTRACT FROM AUTHOR]

A novel snapback-free silicon-controlled rectifier (SFSCR) with P-type Zener implantation (ZP) is developed in a 0.5- $\mu \text{m}$ bipolar CMOS DMOS technology for latch-up immune high-voltage (HV) electrostatic discharge (ESD) protection. The inherent snapback of SCR is successfully suppressed by the novel ZP technique. But, it also brings about a serious degradation in failure current (${I}_{\textsf {t2}}$) when compared with the regular low holding voltage (${V}_{h}$) device. In order to mitigate such degradation, a novel layout terminal is proposed. According to the transmission-line pulse test results, ${I}_{\textsf {t2}}$ of the SFSCR with new layout is increased by 58.5%, while the ON-state resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) is reduced by 48.7% under the same layout area. By comprehensive comparison, the SFSCR is proved to be a potential HV ESD solution. [ABSTRACT FROM AUTHOR]

To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.

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• This paper proposes a novel SCR with high robustness and latch-up immunity. • By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. • Through 2D device simulation, the ESD characteristics of three SCRs are compared. • Vt1 (22.9 V), Vh (13.64 V) and It2 (18.49 A) of the PGSCR meet the requirements of the target chip. In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip. [ABSTRACT FROM AUTHOR]

The low-voltage triggering silicon-controlled rectifier (LVTSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its low trigger voltage and strong current-tolerating capability per area. In this paper, an improved LVTSCR by adding a narrow NWell (NW2) under the source region of NMOS is discussed, which is realized in a 0.5-μm CMOS process. A 2-dimension (2D) device simulation platform and a transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the preliminary LVTSCR, the improved LVTSCR elevates the second breakdown current ( I t 2 ) from 2.39 A to 5.54 A and increases the holding voltage ( V h ) from 3.04 V to 4.09 V without expanding device area or sacrificing any ESD performances. Furthermore, the influence of the size of the narrow NWell under the source region of NMOS on holding voltage is also discussed. [ABSTRACT FROM AUTHOR]

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard. [ABSTRACT FROM AUTHOR]

Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a 0.11~\mu \textm 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure. [ABSTRACT FROM PUBLISHER]

In this paper, an electrostatic discharge ( ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ( Vt) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding n+/p+ floating regions. Moreover, the holding voltage ( Vh) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18-μm bipolar- CMOS- DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the Vt of the proposed circuit increased from 14 V to 27.8 V, and Vh increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V. [ABSTRACT FROM AUTHOR]

This paper proposes an advanced high holding voltage silicon controlled rectifier (AHHVSCR) with a new structure with an insertion of PMOS (P-type metal-oxide-semiconductor). To verify the characteristics of the proposed ESD protection circuit and analyze its operating characteristics, a comparative analysis of electrical characteristics with HHVSCR (High Holding Voltage SCR), was conducted by using TCAD simulation. HBM(Human Body Model) maximum temperature test results confirmed that the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower temperature characteristic than that of HHVSCR (373K), indicating more improved robustness. In addition, the proposed ESD protection circuit was designed by applying N-STACK technology, and its applicability by voltage was verified through simulations. The proposed ESD protection circuit was designed and fabricated using 0.18um BCD process, and the validity of its electrical characteristics was confirmed using TLP (Transmission Line Pulse) system. The proposed ESD protection circuit has improved latch-up immunity with holding voltage of 18.42V, which is 7.7V higher than HHVSCR in a single structure, and it can be applied by voltage with increased holding voltage characteristics of 2-STACK 45.81V and 3-STACK 76.51V according to the application of N-STACK technology. [ABSTRACT FROM AUTHOR]

In order to improve the holding voltage and keep the trigger voltage of the silicon controlled rectifier (SCR) devices, a new self-triggered stacked SCR structure (STSSCR) is proposed for on–chip electrostatic discharge (ESD) protection. The STSSCR structure consists of a modified lateral SCR (MLSCR) and multiple double trigger SCRs (DTSCRs). The trigger voltage of the structure is decided by the trigger voltage of the MLSCR. And the holding voltage is decided by the holding voltage of the SCRs and the number of the DTSCR in the STSSCR structure. The simulation and experimental results show that STSSCR has a stable trigger voltage, a small trigger current and an adjustable high holding voltage. [ABSTRACT FROM AUTHOR]

This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated Bipolar Junction Transistor (BJT) in a 0.18- \mu \textm , 3.3 V process. This device is composed of a floating pMOSFET embedded in a parasitic n-well/p-sub/n+ region BJT structure. The floating pMOS gate is further coupled with an RC network for controlling its switching. The floating pMOS could increase the effective width of its floating p+ region to enhance ESD robustness during ESD zapping events, whereas maintain its floating p+ region narrower during IC operation situation. With the optimized structure dimensions, this device can reach transmission-line pulse second breakdown current 6 A, ESD/ human-body model over 8 kV, which are the same as those of an SCR, and its latchup trigger current is at least 1.9 times greater. [ABSTRACT FROM PUBLISHER]

For high-voltage (HV) applications, the electrostatic discharge (ESD) protection design using a traditional HV device, such as laterally diffused MOSFETs, usually consumes large silicon area to meet sufficient ESD specification. In this paper, an area-efficient ESD protection design with stacked high-holding-voltage silicon-controlled rectifier (HHVSCR) is proposed and verified in a 0.25- \mu \textm 5/60 V Bipolar-CMOS-DMOS process. The proposed HHVSCR is fabricated in low-voltage wells and has the characteristics of HHV and high failure current with the same silicon area as the traditional SCR. From the experimental results, the proposed HHVSCR stacking structure can fit the desired ESD protection design window for the 60 V pins of a battery-monitoring IC and successfully protect these 60 V pins against 7-kV human-body-mode ESD stress. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit -- (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using 0.18 µm Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission- Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A. [ABSTRACT FROM AUTHOR]

In this Letter, an enhanced bidirectional modified lateral silicon‐controlled rectifier (EBMLSCR) is proposed for advanced dual‐directional electrostatic discharge (ESD) protection applications. The ESD characteristics of the novel EBMLSCR and conventional bidirectional modified lateral silicon‐controlled rectifier (BMLSCR) are measured using the transmission line pulsing tester. Compared with the BMLSCR, the EBMLSCR owns a lower trigger voltage down to 7.7 V, a higher failure current up to 6.5 A, a suitable holding voltage as well as the same superior leakage current. Based on these advantages, the proposed EBMLSCR can provide an effective ESD protection for the advanced 2.5 V/3.3 V input/output circuits, while the traditional BMLSCR becomes invalid for these applications due to its high trigger voltage and low robustness. In addition, the impact of some critical dimensions of the EBMLSCR has also been evaluated to further optimise the device performances. [ABSTRACT FROM AUTHOR]

• The holding voltage of the ADDSCR is increased by inserting floating heavy doping in the base region NW of the parasitic transistor PNP and PW of the parasitic transistor NPN under the condition that the device dimension and other factors remain the same. • The effects of various floating heavy doping combinations on the current path and lattice temperature of the device are analyzed through two-dimensional device simulation. • TLP test data were used to compare various floating heavy doping combinations, and the DC characteristics and capacitance of the devices were tested. • Five types of ADDSCR devices were fabricated in 0.18 μm BCD process with high failure current and high hold voltage, which can be applied to ESD protection between CAN pins and GND in automotive chips. In the ESD protection design work, the most effective way to improve the holding voltage of bidirectional silicon-controlled rectifier or SCR device is to increase the distance between the cathode and anode of it. However, for DDSCR devices with multi-finger layouts, increasing this distance will result in a decrease in failure current and require a larger layout area. In this work, five types of asymmetric dual direction silicon-controlled rectifier devices with different floating heavy doping combinations are designed based on the traditional ADDSCR structure. Meanwhile, the dimensions, number of fingers, metal layout and number of CONT holes of the five ADDSCR structures are strictly kept the same, aiming at studying the influence of different floating heavy doping combinations on the performance of SCR devices and find the optimal floating heavy doping combination. Their ESD performances are predicted and verified through the two-dimensional device simulations and transmission line pulse (TLP) test results. All the five types of ADDSCR structures are designed to improve the holding voltage. From the results, the forward and reverse holding voltage of ADDSCR_PP, which is inserted floating P+ in NW and PW, are increased to 20.4 V and 17.6 V respectively, compared with the traditional devices without floating heavy doping at 14.2 V and 8.7 V. At the same time, the physical mechanism for the effect of floating heavy doping insert into NW and PW separately were investigated. Finally, the one that best meets the ESD window of automotive application is found. [ABSTRACT FROM AUTHOR]

A MOS–IGBT–SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch-up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this work. The drift area, the form factor, and the proportion of P + sections inserted into the drain are the main parameters, which have a significant impact on the latch-up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V. [ABSTRACT FROM AUTHOR]

In this paper, a novel SCR (Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. The proposed protection circuit has high holding voltage due to floating n+ region which reduces current gain of parasitic bipolar transistor. This characteristic makes it ensure latch-up immunity. The electrical characteristics of the proposed ESD protection circuit have been simulated by using Synopsys TCAD simulation tool. According to the simulation results, the proposed protection circuit has high holding voltage of about 4.61 V to 8.75 V as design variation. Also, it is verified by using TLP (Transmission Line Pulse) system. As a result of measurement, it has holding voltage of 15.7V to 19.35V as design variation and high robustness above HBM 6kV, MM 600V. [ABSTRACT FROM AUTHOR]

Gate-grounded NMOS (ggNMOS) transistors have widely served as electro-static discharge (ESD) protection devices for integrated circuits. The layout strategy of ggNMOS greatly influences its ESD protection characteristics. Layout strategies forvariation of the number of substrate-pickup stripes are investigated in this paper. Direct current and transmission-line pulsing test results are presented to verify that adjustable holding voltages are accessed by variation of the number of substrate-pickup stripes. The design with two evenly distributed substrate-pickup stripes among different fingers is found to exhibit the highest second break current and optimal width-scaling characteristics. [ABSTRACT FROM AUTHOR]

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using 0.18 µm Bipolar-CMOS-DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008). [ABSTRACT FROM AUTHOR]

In this letter, by utilizing the unique property of large hysteresis of threshold selector, a novel operation scheme is proposed to not only lower the voltages and power, but also remove the voltage matching constrains between resistive memory (RRAM) and selector. This makes threshold selector suitable for most of RRAM integration. [ABSTRACT FROM PUBLISHER]

Due to latch-up issue, the main problem of silicon-controlled rectifier (SCR) for power supply clamps in on-chip ESD protection is its inherent low holding voltage, especially in high-voltage applications. In this paper, we proposed a MOS-inside SCR (MISCR) showing nearly no snapback character and good ESD robustness, which is qualified for on-chip power clamp ESD protection. The stacked device achieves a series of triggering and holding voltage by altering the stacking number, which can also be used for the high voltage ESD power supply clamp applications. [ABSTRACT FROM AUTHOR]

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.1 8um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated. [ABSTRACT FROM AUTHOR]

A silicon-controlled rectifier (SCR)-incorporated BJT with high holding voltage is developed for electrostatic discharge (ESD) protection in a 0.6 \mu\m high-voltage 10 V process. This device consists simply of a floating \P^+ diffusion incorporated in a parasitic NPN BJT. A robust 6–7 kV ESD threshold and high-latchup-immune holding voltage of 15–18 V can be achieved by layout optimization of the NPN- \N^+-collector to floating \P^+-diffusion spacing and the floating \P^+ diffusion width. It can be equivalently regarded as parallel connection of an incorporated PNPN SCR part and an NPN BJT part. The incorporated SCR part is further composed of a parasitic SCR in series with a reverse-biased PN diode formed by the floating \P^+ region and N-well. The further analysis shows that the floating \P^+ diffusion is the key part of this SCR-incorporated BJT. The parasitic reverse-biased PN diode sustains most of the high holding voltage. The parasitic NPN BJT plays a major role in ESD current conduction, while the incorporated SCR in series with the reverse-biased PN diode is the secondary conduction path. [ABSTRACT FROM PUBLISHER]

The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions. [ABSTRACT FROM PUBLISHER]

In this letter, a novel high latch-up immunity electrostatic discharge protection device that can be equivalent to a PNP-type bipolar junction transistor (BJT) and a series-connected Zener diode is proposed. For the proposed device, the emitter of its BJT is formed by Zener implantation instead of conventional P-plus. In this way, the high latch-up immunity can be achieved by the Zener implantation dose and window designing. Meanwhile, the proposed device exhibits excellent voltage clamp capability and 2.2 times large second breakdown current as a generally used diode. [ABSTRACT FROM PUBLISHER]

Abstract: The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8V and a high trigger current of greater than 120mA. The robustness has measured to HBM 8kV (HBM: human body model) and MM 400V (MM: machine model). The proposed device has a high-level It2 of 52mA/μm approximately. [Copyright &y& Elsevier]