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Most state-of-the-art compression algorithms use complex connectivity traversal and prediction schemes, which are not efficient enough for online compression of large meshes. In this paper we propose a scalable massively parallel approach for compression and decompression of large triangle meshes using the GPU. Our method traverses the input mesh in a parallel breadth-first manner and encodes the connectivity data similarly to the well known cut-border machine. Geometry data is compressed using a local prediction strategy. In contrast to the original cut-border machine, we can additionally handle triangle meshes with inconsistently oriented faces. Our approach is more than one order of magnitude faster than currently used methods and achieves competitive compression rates.

The title of this three-volume set on graphics from Romania, ‘Graphics without Computers’, makes a strong statement. It attracts attention, but, in its ambiguity, is misleading for two reasons. Fir...

Graphics are additional elements of vehicle design where even their absence is also an important part of their design. This chapter deals with the arts, science, and mathematics of graphics and their impact on vehicle character.

This paper describes the implementation of high performance process simulator clusters based on modern graphical processing unit architectures. Graphics rendering is basically just an intensive session of complex mathematical calculations, reading and writing memory buffers and computing bitmap matrixes. This is extremely similar to what system simulation software actually does: some mathematics - less complex than the usual graphics rendering in a typical 3D game, updating some algorithm state variables held in memory, and computing an output for the system. The first part of this article will focus on comparing hardware architectures between the central processing unit and graphics processing unit, and the second part will focus on implementing a PID controller on both. A case study will be presented in the last part, presenting a highly efficient mobile application which will employ the on-board graphics processing unit to provide system simulations while also saving energy.

A parallel single-instruction multiple data implementation of a two-level nested loop, which uses shared memory, is implemented via general-purpose computing on a graphics processing unit. The general-purpose computing on a graphics processing unit implementation is compared to MATLAB®, C, and other implementations of the same algorithm, which are primarily executed on the central processing unit. The general-purpose computing on a graphics processing unit implementation is determined to be decisively faster (80 times) than the fastest single threaded implementation. A linear algebra implementation is determined to consume excessive memory without a corresponding increase in computational performance. Although the speedup is hardware dependent, the general-purpose computing on a graphics processing unit algorithm exploits cache memory in a manner that is severely constrained on conventional multicore central processing units. For this reason, the nested loop described here is a natural fit for the single-...

Current graphics processing units (GPU) typically offer only a limited number of programmable pipeline stages, whose usage, data flow and topology are mostly fixed. Although a more flexible, custom rendering pipeline can be emulated using the compute functionality of existing GPUs, this approach requires to manage work queues, synchronization, and scheduling in software. In this paper, we present a hardware architecture for a novel, programmable rendering pipeline, which is based on a circulating stream of data and control tokens that are iteratively modified via pattern matching. Our architecture provides light-weight mechanisms for dynamic thread creation, lock-free synchronization, and scheduling to support recursion, dynamic shader linkage and custom primitive types. A hardware prototype, running complex examples, demonstrates the improved reconfigurability also the scalability of our graphics architecture.

Bidirectional Texture Functions (BTFs) are among the highest quality material representations available today and thus well suited whenever an exact reproduction of the appearance of a material or complete object is required. In recent years, BTFs have started to find application in various industrial settings and there is also a growing interest in the cultural heritage domain. BTFs are usually measured from real-world samples and easily consist of tens or hundreds of gigabytes. By using data-driven compression schemes, such as matrix or tensor factorization, a more compact but still faithful representation can be derived. This way, BTFs can be employed for real-time rendering of photo-realistic materials on the GPU. However, scenes containing multiple BTFs or even single objects with high-resolution BTFs easily exceed available GPU memory on today’s consumer graphics cards unless quality is drastically reduced by the compression. In this paper, we propose the Bidirectional Sparse Virtual Texture Function, a hierarchical level-of-detail approach for the real-time rendering of large BTFs that requires only a small amount of GPU memory. More importantly, for larger numbers or higher resolutions, the GPU and CPU memory demand grows only marginally and the GPU workload remains constant. For this, we extend the concept of sparse virtual textures by choosing an appropriate prioritization, finding a trade off between factorization components and spatial resolution. Besides GPU memory, the high demand on bandwidth poses a serious limitation for the deployment of conventional BTFs. We show that our proposed representation can be combined with an additional transmission compression and then be employed for streaming the BTF data to the GPU from from local storage media or over the Internet. In combination with the introduced prioritization this allows for the fast visualization of relevant content in the users field of view and a consecutive progressive refinement.

Within this paper, we present a novel, straightforward progressive encoding scheme for general triangle soups, which is particularly well-suited for mobile and Web-based environments due to its minimal requirements on the client's hardware and software. Our rapid encoding method uses a hierarchy of quantization to effectively reorder the original primitive data into several nested levels of detail. The resulting stateless buffer can progressively be transferred as-is to the GPU, where clustering is efficiently performed in parallel during rendering. We combine our approach with a crack-free mesh partitioning scheme to obtain a straightforward method for fast streaming and basic view-dependent LOD control.

In order to render 3-D graphics efficiently, rasterization techniques have been developed. Traditional clipping techniques using six-planes of view volume are complicated and not cost-effective. This paper develops a novel cost-effective strategy for primitives with regard to clipping in rasterization. Throughout the process, no expensive clipping action is required and no extra clipping-derived polygons are produced. It also presents the architecture of a 200-MHz multicore, multi-thread 3-D graphics SoC in 65nm 1P9M process with a core size of 4.97mm2 and 153.3mW for power consumption. The proposed clip-less architecture in rasterization processes the valid screen space region of each primitive in eight cycles, with a gate-count of only 20k. In addition, the throughput can achieve up to 25 M Triangles/Sec.

Embedded systems in several applicationsrequire a graphics system to displaysome application-specific information. Yet, commercial graphic cards for the embedded systems either incur high costs, or they are inconvenient to use. Furthermore, they tend to quickly become obsolete due to the advances in display technology. On the other hand, FPGAs provide reconfigurable hardware resources that can be used to implement graphics system in which they can be reconfigured to meet the ev er-evolving requirements of graphics systems. Motivated from this fact, this study considers the design and implementation of a 2D graphics system on FPGA. The graphics system proposed is composed of a CPU IP core, peripheral IP cores (Bresenham, BitBLT, D DR Memory Controller, and VGA) and PLB bus to which CPU and all peripheral IP cores are attached. Furthermore, some graphics drivers and APIs are developed to complete the whole graphics creation process.

In many scientific and engineering applications, the solution of large sparse systems of equations is one of the most important stages. For this reason, many libraries have been developed among which ILUPACK stands out due to its efficient inverse-based multilevel preconditioner. Several parallel versions of ILUPACK have been proposed in the past. In particular, two task-parallel versions, for shared and distributed memory platforms, and a GPU accelerated data-parallel variant have been developed to solve symmetric positive definite linear systems. In this work we evaluate the combination of both previously covered approaches. Specifically, we leverage the computational power of one GPU (associated with the data-level parallelism) to accelerate each computation of the multicore (task-parallel) variant of ILUPACK. The performed experimental evaluation shows that our proposal can accelerate the multicore variant when the leaf tasks of the parallel solver offer an acceptable dimension.

This document demonstrates an efficient stroke algorithm to be used for drawing maps. Map data is stored in vector graphics format and before the actual draw operation items are scaled, cap and joint types defined in map style are added. Proposed stroke algorithm is benchmarked against Anti-Grain Geometry graphics library using both basic vector shapes and real OpenStreet Map (OSM) map data. It is demonstrated that proposed stroke algorithm can create data, ready to be fed to modern graphic acceleration hardware faster without significant quality loss.

Recent developments in the design of graphics processing units (GPUs) have been occurring at a much greater pace than with central processor units (CPUs) and very powerful processing units have been designed solely for the processing of computer graphics. For instance, the Tesla® K40 GPU includes 2,880 cores and 12 GB memory, and it can reach to 4.29 Tflops peak single precision floating point performance. Due to this potential in faster computations, the GPUs have received the attention of the scientific computing community. Initially these cards were designed for computer graphics and floating precision arithmetic has been sufficient for such applications. Due to the demand of higher precision arithmetic from the scientific community, the vendors have started to develop graphics cards that support double precision arithmetic as well by introducing a new generation of graphical computation cards.

AMD's first Fusion Accelerated Processor Unit (APU) codenamed “Zacate” (Fig. 15.4.1) combines a pair of x86 CPUs cores codenamed “Bobcat”, 1MB L2 Cache, Client Northbridge (CNB), with a DirectX® 11 Radeon™ HD5000 graphics/multimedia controller on a single die. The CNB provides an interface to a single 64b DDR3 memory channel, which can operate at up to DDR3–1066. The Fusion architecture implements an efficient form of unified memory architecture (UMA) where a portion of system memory is reserved as graphics frame buffer memory. The graphics memory controller (GMC) arbitrates between graphics, video and display memory accesses and presents a well-ordered stream of system memory requests through the CNB over dedicated 256b wide read and write busses. These GMC requests bypass all of the CNB coherency mechanisms allowing for fast direct access to memory and exposing most of the available memory bandwidth (8.53GB/s). Compared to two chip solutions, use of the on-die integrated GPU significantly reduces memory latency, improves request ordering, and reduces power. The APU supports display formats including VGA, LVDS, Display Port, DVI or HDMI™. A ×4 Gen2 PCIe® Unified Media Interface (UMI) to an external Fusion Controller Hub (FCH) is supported for system I/O. An additional 4× PCIe Gen2 link supports I/O to external Discrete Graphics chip.

This paper presents a fully programmable 3-D graphics processor using unified shaders for mobile environment. In the system level, we adopted dual-core, dual-issue VLIW, and multithreading methods to utilize instruction, data, and task level parallelism in the graphics applications. In the shader core level, a novel IEEE-754 compliant 4-D vector inner product arithmetic unit and a configurable texture cache are proposed. Using these methods, the proposed processor achieves 143 Mvertices/s and 2.3 Gtexels/s consuming the power of 367 mW. The evaluation shows significant performance and power-delay product benefits. For real graphics applications, test results indicate 2.07 times improvement in performance and 34% reduction in power-delay product compared to previous mobile 3-D graphics processors. The proposed 3-D graphics processor is implemented in 4.5× 4.52 mm using 0.18 μm CMOS technology.

Although modern graphics processing units (GPU) contain a large number of programmable shader cores, the focus on data parallelism and also the lack of efficient on-chip communication hinder the creation of custom graphics pipelines with arbitrary topologies. Based on the concept of stream rewriting, we propose a novel many-core architecture for graphics processing, which supports dynamic scheduling of recursively expandable task graphs and graphics pipelines. In particular, the tasks and their dependencies are encoded as a token stream, which is iteratively rewritten via pattern matching on multiple cores in parallel. The scalability of the proposed hardware architecture has been evaluated using an FPGA prototype.

A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.

A full 3D graphics pipeline is investigated, and optimizations of graphics architecture are assessed for satisfying the performance requirements and overcoming the limited system resources found in mobile terminals. Two mobile 3D graphics processor architectures, RAMP and DigiAcc, are proposed based on the analysis, and a prototype development platform (REMY) is implemented. REMY includes a software graphics library and simulation environment developed for more flexible realization of mobile 3D graphics. The experimental results demonstrate the feasibility of mobile 3D graphics with 3.6 Mpolygons/s at 155 mW power consumption for full 3D operation.

We present a new, unified approach to debugging graphics software. We propose a representation of all graphics state over the course of program execution as a relational database, and produce a query-based framework for extracting, manipulating, and visualizing data from all stages of the graphics pipeline. Using an SQL-based query language, the programmer can establish functional relationships among all the data, linking OpenGL state to primitives to vertices to fragments to pixels. Based on the Chromium library, our approach requires no modification to or recompilation of the program to be debugged, and forms a superset of many existing techniques for debugging graphics software.

We present two implementations of a view-independent cell projection algorithm for off-the-shelf programmable graphics hardware. Both implementations perform all computations for the projection and scan conversion of a set of tetrahedra on the graphics hardware and are therefore compatible with many of the hardware-accelerated optimizations for polygonal graphics, e.g., OpenGL vertex arrays and display lists. Apart from our actual implementations, we discuss potential improvements on future, more flexible graphics hardware and applications to interactive volume visualization of unstructured meshes.

Currently, memory bandwidth has become the main bottleneck in graphics system. Reducing the memory access can reduce the power consumption and boost overall system performance. Low power technique is more important for graphics applications on hand-held or mobile device. In this paper, we propose a novel visibility driven rasterizer to reduce the memory access and operations on invisible pixels. It integrates with two-level hierarchical Z-buffer to do visibility driven rasterization. The rasterization scheme is tile-order scan-line based, and the rasterizer can smartly change the tile-size depending on the triangle size. This technique can balance the rasterization loading under different triangles. Moreover, we propose a fast visibility test algorithm to quickly reject a group of pixels within the tile. Simulation results show that the overall bandwidth reduction can be up to 60% under our test images.

The earliest Web browsers focussed on the display of textual information. When graphics were added, essentially only image graphics and image file formats were supported. For a significant range of applications, image graphics has severe limitations, for example in terms of file size, download time and inability to interact with and modify the graphics client-side. Vector graphics may be more appropriate in these cases, and this has become possible through the introduction of the WebCGM and Scalable Vector Graphics (SVG) formats, both of which are open standards, the former from ISO/IEC and W3C and the latter from W3C. This paper reviews the background to Web graphics, presents the WebCGM file format, and gives a more detailed exposition of the most recent format, SVG. The paper concludes with reflections on the current state of this area and future prospects.

More and more 2D graphics engines are extended with GPU accelerated code paths to share the workload between the CPU and GPU. This becomes even more important on embedded systems which are resource constrained. In the following, we present the GL2D engine, which is optimized for GPUs with OpenGL ES 2.0 support.

In this digital world, more than 90% of desktop and notebook computers have integrated Graphics Processing Units i.e. GPU's, for better graphics processing. Graphics Processing Unit is not only for graphics applications, even for non-graphics applications too. In the past few years, the graphics programmable processor has evolved into an increasingly convincing computational resource. But GPU sits idle if graphics job queue is empty, which decreases the GPU's efficiency. This paper focuses on various tact to overcome this problem and to make the CPU-GPU processing more powerful and efficient. The graphics programmable processor or Graphics processing unit is especially well suited to address problem sets expressed as data parallel computation with the same program executed on many data elements concurrently. The objective of this paper is to increase the capabilities and flexibility of recent GPU hardware combined with high level GPU programming languages: to accelerate the building of images in a frame buffer intended for output to a display, and, to provide tremendous acceleration for numerically intensive scientific applications. This paper also gives some light on major applicative areas where GPU is in use and where GPU can be used in future.

Everybody has their own favorite bunch of programming tricks. A few years ago, I started the Graphics Gems series of books to bring together lots of these handy techniques. The Journal of Graphics Tools (http://www.acm.org/jgt) has continued that tradition. In this column, I thought I would describe some little tricks of mine that are too small even for JGT. Small can be beautiful. Most of these techniques are so useful that I have bundled them up into little libraries. They include: the amazing expando-square, blob functions and multipoint weighting.

Two vector units embedded in the emotion engine chip support high-quality 3D graphics, emotion synthesis, and 300-MHz, 5.5-GFLOPS operation for the recently introduced PlayStation2 game entertainment system.

PCs with substantial 3D graphics are arriving on desktops everywhere. It was only a few years ago that people sniggered at PC graphics and laughed out loud at the notion of PCs with robust and versatile operating systems. Now, however, PC operating systems-especially Windows NT-have software development, networking, multiprocessing, and other tools to rival Unix environments. A user or developer can add a 3D graphics accelerator offering pipelined rendering, full texture mapping, and a complete set of graphics tools with performance that competes with mid-range graphics workstations. And no one is going to beat the price point. On top of all this, it's clear that Intel and Microsoft take this market seriously.

On various consumer electronics devices including smart phones and table PC's, the 3D graphics architectures are rapidly changing from fixed function pipelines to programmable pipelines. To execute the traditional graphics applications on the modern programmable pipelines, shader programs are used for their emulations. In this paper, we present an efficient way of the most suitable shader program generation for the given configurations. Comparing to the previously used shader programs, our just-in-time approach shows remarkable speed-ups, to give much more convenience for their consumers.

• High performance, but power efficient, and very low power modes • AV in and out media hub • Specialized audio, graphics, and video processors offload CPU and graphics core • CPU, GPU, specialized processors, and 10 share memory via host-guest MMUs with synchronized page tables • High bandwidth CPU cache coherency • 200+ GB/second power efficient memory system balanced to CPU, GPU, specialized processors, and 10 requirements • DX11.1+ graphics core with custom graphics and compute command processors to offload CPU and improve GPGPU

This paper presents a tactile hard-copy system which help an "active tactile graphics" for the blind. Here the word "active" means that the blind can make graphics programs and deal with computer graphics by his own efforts. It translates the color graphics on the screen into an embossed dots image on paper. To get a precise embossed dots hard-copy close to the real graphics screen, we adopted a Braille printer plotter. The program stays resident in computer's memory, and a push of COPY key at any time starts to make an embossed hard-copy of the current graphic screen. By this system and computer language like C, the blind can try to make graphics programs and examine the colors and the graphic figures constructing the screen graphics. The system can extract several combinations of colors from the whole graphics selectively and make the hard-copys. This color selective hard-copys help the blind understand the whole graphics as a result, because each hard-copy reduces the complexity of the graphics and tends to be easier to examine by touch.

Increasingly, 3D graphics is becoming the rule rather than the exception in applications such as games, CAD/CAM, and video production. Some LSIs provide rendering capabilities, but require an additional CPU to perform essential geometry transformations. Fujitsu's chip set solves that problem using two processors to render 300,000 polygons per second (for flat-shaded triangles with texture)-performance comparable to that of advanced game machines.

The Siggraph/Eurographics Graphics Hardware 2003 workshop, held in San Diego, will likely be remembered as a turning point in modern computing. In one of those rare moments when a new paradigm visibly begins changing general-purpose computing's course, what has traditionally been a graphics-centric workshop shifted its attention to the nongraphics applications of the graphics processing unit. GPUs, made by Nvidia (www.nvidia.com) and ATI (www.ati.com), function as components in graphics subsystems that power everything from Microsoft's Xbox to high-end visualization systems from Hewlett-Packard and SGI. The GPUs act as coprocessors to CPUs such as Intel's Pentium, using a fast bus such as Intel's Advanced Graphics Port. AGP8x has a peak bandwidth of 2.1 gigabytes per second - speed it needs to avoid inflicting bus starvation on data-hungry GPU coprocessors.

To resolve the difficulty of reading and identifying the CAD graphics file about automatic distinguishing and judging of CAD graphics file, this paper propses a CAD graphics identification method based on the graphics primitive. In this method, the CAD graphics is exploded to graphics primitive and read the graphics attribute. According to the comparison results of the identified graphics and standard graphics, the graphics primitives are differentiated with their graphics attributs. The graphics identification is finished by reading different sorts of graphics primitives.

This paper attempts to introduce a model for three-dimensional computer graphics in personal computers (PC). It introduces a design based on the Programmers Hierarchical Interactive Graphics System (PHIGS) and suggests some methods for achieving this design on PCs.

Recent applications of computer software to water resources and environmental master-planning studies include use of graphical displays in order to disseminate information. In this paper, a simple-to-use graphics display program is presented which enables a user to display graphical slides, stored on disk, to the CRT. Such a program enables a user to link graphics slides to next data by use of a read-only text display routine. Application of the provided program in a Graphics Data Base Management System is considered as a case study. Computer code is provided for the graphics slide display.

In the past few years, parallel processing has been the driving force behind improving performance. Instead of faster clocked processors, new generations of Intel or AMD processors provide more parallelism. Likewise, graphics processors also rely on a network of multiple cores or parallelism to accelerate computations involved in rendering graphics. This research examines the application of general purpose processing on graphics processors. The development process and programming effort of translating a side lobe minimization imaging algorithm to a graphics processing units (GPU) are considered for analysis. The purpose is to acquire a sufficient amount of experience and data to determine the feasibility of deploying a graphics card-complemented system for tactical and high performance computations.

In many ways, 3D graphics and vision processing are inverse operations. Graphics processing generates pixels from descriptors, while vision generates descriptors from pixels [1]. Since augmented reality (AR) requires both graphics and vision abilities (Fig. 18.6.1), we report a unified processor for graphics, vision, and pose estimation for marker tracking. To process both graphics and vision simultaneously, we use 4 key features: (1) 6-way VLIW datapath design of processing elements, (2) reconfigurable processing elements for graphics and vision modes, (3) a pixel arranger for vision processing that has the inverse characteristic of a graphics rasterizer, and (4) a dedicated pose-estimation engine to generate graphics control data from vision processing. Using these methods, we achieve 371.9GOPS/W for full operation in a VGA image and 0.89µW/fps for pose estimation.

In this chapter, we will explore one of the most remarkable aspects of the iPhone: its unique ability to switch seamlessly between one view and another. We have all seen the wonderful iPhone and iPad ads on television, in which a person’s fingers direct an amazing flow of vivid images, within interactive applications, and cause one view to just slide or roll directly into another, giving the impression of performance art. The concept behind this is what Apple calls Switch View methodology. As a professor of computer science, I have learned of several pitfalls regarding the teaching—and learning—of the Switch View methodology.

In this chapter, we explore the implementation of fault table generation on a graphics processing unit (GPU). A fault table is essential for fault diagnosis and fault detection in VLSI testing and debug. Generating a fault table requires extensive fault simulation, with no fault dropping, and is extremely expensive from a computational standpoint.

As we discussed in Chap. 14, “Graphics Overview,” the ggplot2 package is an implementation of Wilkinson’s grammar of graphics (hence the “gg” in its name). The last chapter focused on R’s traditional graphics functions. Many plots were easy, but other plots were a lot of work compared to SAS or SPSS. In particular, adding things like legends and confidence intervals was complicated.