Back to Search
Start Over
A Low-Power Integrated x86–64 and Graphics Processor for Mobile Computing Devices
- Source :
- ISSCC
- Publication Year :
- 2012
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2012.
-
Abstract
- AMD's first Fusion Accelerated Processor Unit (APU) codenamed “Zacate” (Fig. 15.4.1) combines a pair of x86 CPUs cores codenamed “Bobcat”, 1MB L2 Cache, Client Northbridge (CNB), with a DirectX® 11 Radeon™ HD5000 graphics/multimedia controller on a single die. The CNB provides an interface to a single 64b DDR3 memory channel, which can operate at up to DDR3–1066. The Fusion architecture implements an efficient form of unified memory architecture (UMA) where a portion of system memory is reserved as graphics frame buffer memory. The graphics memory controller (GMC) arbitrates between graphics, video and display memory accesses and presents a well-ordered stream of system memory requests through the CNB over dedicated 256b wide read and write busses. These GMC requests bypass all of the CNB coherency mechanisms allowing for fast direct access to memory and exposing most of the available memory bandwidth (8.53GB/s). Compared to two chip solutions, use of the on-die integrated GPU significantly reduces memory latency, improves request ordering, and reduces power. The APU supports display formats including VGA, LVDS, Display Port, DVI or HDMI™. A ×4 Gen2 PCIe® Unified Media Interface (UMI) to an external Fusion Controller Hub (FCH) is supported for system I/O. An additional 4× PCIe Gen2 link supports I/O to external Discrete Graphics chip.
- Subjects :
- Coprocessor
CPU cache
Computer science
Graphics processing unit
Registered memory
computer.software_genre
CAS latency
law.invention
Non-uniform memory access
Shared memory architecture
CUDA Pinned memory
law
Memory architecture
Interleaved memory
Graphics address remapping table
Electrical and Electronic Engineering
Memory refresh
Computer memory
Conventional memory
Dynamic random-access memory
Hardware_MEMORYSTRUCTURES
business.industry
Uniform memory access
Semiconductor memory
Memory bandwidth
Memory controller
Extended memory
Operating system
Multi-channel memory architecture
x86
Central processing unit
business
computer
Computer hardware
Subjects
Details
- ISSN :
- 1558173X and 00189200
- Volume :
- 47
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........a93c87f90538d45277f003f9efed17b7
- Full Text :
- https://doi.org/10.1109/jssc.2011.2167776