Search

The growth of crystalline Li-based oxide thin films on silicon substrates is essential for the integration of next-generation solid-state lithionic and electronic devices including on-chip microbatteries, memristors, and sensors. However, growing crystalline oxides directly on silicon typically requires high temperatures and oxygen partial pressures, which leads to the formation of undesired chemical species at the interface compromising the crystal quality of the films. In this work, we employ a 2 nm gamma-alumina (γ-Al

We investigate differential evolution optimization to fit Rutherford backscattering data. The algorithm helps to find, with very high precision, the sample composition profile that best fits the experimental spectra. The capabilities of the algorithm are first demonstrated with the analysis of synthetic Rutherford backscattering spectra. The use of synthetic spectra highlights the achievable precision, through which it becomes possible to differentiate between the counting statistical uncertainty of the spectra and the fitting error. Finally, the capability of the algorithm to analyze large sets of experimental spectra is demonstrated with the analysis of the position-dependent composition of a Sr[Formula: see text]Ti[Formula: see text]O[Formula: see text] layer on a 200 mm silicon wafer. It is shown that the counting statistical uncertainty as well as the fitting error can be determined, and the reported total analysis uncertainty must cover both.

The radionuclide thorium-229 features an isomer with an exceptionally low excitation energy that enables direct laser manipulation of nuclear states. It constitutes one of the leading candidates for use in next-generation optical clocks$^{1–3}$. This nuclear clock will be a unique tool for precise tests of fundamental physics$^{4–9}$. Whereas indirect experimental evidence for the existence of such an extraordinary nuclear state is substantially older$^{10}$, the proof of existence has been delivered only recently by observing the isomer’s electron conversion decay$^{11}$. The isomer’s excitation energy, nuclear spin and electromagnetic moments, the electron conversion lifetime and a refined energy of the isomer have been measured$^{12–16}$. In spite of recent progress, the isomer’s radiative decay, a key ingredient for the development of a nuclear clock, remained unobserved. Here, we report the detection of the radiative decay of this low-energy isomer in thorium-229 ($^{229m}$Th). By performing vacuum-ultraviolet spectroscopy of $^{229m}$Th incorporated into large-bandgap CaF$_{2}$ and MgF$_{2}$ crystals at the ISOLDE facility at CERN, photons of 8.338(24) eV are measured, in agreement with recent measurements$^{14–16}$ and the uncertainty is decreased by a factor of seven. The half-life of $^{229m}$Th embedded in MgF$_{2}$ is determined to be 670(102) s. The observation of the radiative decay in a large-bandgap crystal has important consequences for the design of a future nuclear clock and the improved uncertainty of the energy eases the search for direct laser excitation of the atomic nucleus. The nucleus of the radioisotope thorium-229 (${}^{229}$Th) features an isomer with an exceptionally low excitation energy that enables direct laser manipulation of nuclear states. For this reason, it is a leading candidate for use in next-generation optical clocks. This nuclear clock will be a unique tool, amongst others, for tests of fundamental physics. While first indirect experimental evidence for the existence of such an extraordinary nuclear state is significantly older, the proof of existence has been delivered only recently by observing the isomer's electron conversion decay and its hyperfine structure in a laser spectroscopy study, revealing information on the isomer's excitation energy, nuclear spin and electromagnetic moments. Further studies reported the electron conversion lifetime and refined the isomer's energy. In spite of recent progress, the isomer's radiative decay, a key ingredient for the development of a nuclear clock, remained unobserved. In this Letter, we report the detection of the radiative decay of this low-energy isomer in thorium-229 (${}^{229\mathrm{m}}$Th). By performing vacuum-ultraviolet spectroscopy of ${}^{229\mathrm{m}}$Th incorporated into large-bandgap CaF${}_2$ and MgF${}_2$ crystals at the ISOLDE facility at CERN, the photon vacuum wavelength of the isomer's decay is measured as 148.71(42) nm, corresponding to an excitation energy of 8.338(24) eV. This value is in agreement with recent measurements, and decreases the uncertainty by a factor of seven. The half-life of ${}^{229\mathrm{m}}$Th embedded in MgF${}_2$ is determined to be 670(102) s. The observation of the radiative decay in a large-bandgap crystal has important consequences for the design of a future nuclear clock and the improved uncertainty of the energy eases the search for direct laser excitation of the atomic nucleus.

We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity ( $\rho _{\text {c}}$ ) of Mo/n-InGaAs contact clearly outperforms after annealing. However, for the first time, we demonstrate that the Mo/Pd (2nm)/n-InGaAs contact can achieve a $\rho _{\text {c}}~35$ % and 20% lower than a single Mo/n-InGaAs contact after annealing at 400 °C and 450 °C for 1min, respectively.

With the slowing down of Moore’s law, related to conventional scaling of integrated circuits, alternative technologies will require research effort for pushing the limits of new generations of electronic or photonic devices. Perovskite oxides with the ABO3 chemical formula have a very wide range of interesting intrinsic properties such as metal-insulator transition, ferroelectricity, pyroelectricity, piezoelectricity, ferromagnetic and superconductivity. For the integration of such oxides, it is of great interest to combine their properties with traditional electronic, memory and optical devices on the same silicon-based platform. In the context of high-speed chip-to-chip optical interconnects, compact high-resolution beam steering and video-rate RGB hologram generation require the integration of fast and efficient optical modulators on top of silicon CMOS devices. For these applications the integration of high quality electro-optical materials A defect-free material-stack deposition on silicon wafers is hence required. Among the possible materials options, barium titanate (BaTiO3) is one promising candidate due to its large intrinsic Pockels coefficients that can be obtained. In a first part of the talk, we will review the different options to integrate BaTiO3 on Silicon substrate though different templates to control the polarization direction and discuss the influence on the physical, electrical and optical properties. Then in the second section we will discuss the use of perovskites oxide in the field of topological based qubits which is one of the promising methods for realizing fault-tolerant computations. It is recognized that superconductor/topological insulator heterostructure interfaces may be a perfect host for the exotic “Majorana” particles. These have relevant topological protection nature as required for processing information. Therefore, the physics at the superconductor/topological insulator heterostructure interface need to be studied further, starting at the material level. In this work, a candidate material Barium Bismuthate (BBO) is studied utilizing the Oxide Molecular Beam Epitaxy (MBE) process. The perovskite structure provides opportunity for easily tailored functionality through substitutional doping. Incorporation of potassium into the lattice of BBO results in a superconducting phase with Curie temperature as high as ~ 30K. In addition, BBO is according to DFT based studies, predicted to form topological surface states when doped with Fluorine. In our work, we integrate BBO perovskite on Si(001) substrate, using an epitaxially grown strontium titanate (STO) single-crystalline buffer layer and discuss the structural and chemical properties of the heterostructure will be established by utilizing physical characterization techniques such as AFM, and TEM in later stages. This will go hand in hand with the understanding of the ARPES studies and related surface reconstruction of BBO observed by RHEED as a criterion for the high-quality films. This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation program (grant agreements No 864483 and 742299)”.

Herein, the carrier lifetime in approximately 5x10^16 cm^(-3) n-doped In(x)Ga(1-x)As layers is studied by diode current–voltage analysis and by time-resolved photoluminescence. Two sets of hetero-epitaxial layers are grown on semi-insulating InP or GaAs substrates. The first set corresponds with a constant In content p + n stack, while the second set has a fixed x = 0.53 for the n-layer, while containing various extended defect densities by using a strain relaxed buffer with different x. This results in threading dislocation densities (TDDs) between approximately 10^5 cm^(-2) and a few 10^9 cm^(-2). It is shown that the overall trend of the recombination lifetime versus TDD can be described by a first-order model considering a finite recombination lifetime value inside a dislocation core of 1 nm. For the generation lifetime, a strong electric-field enhancement factor is found. Also, the residual strain in the n-layer has an impact. Overall, the safe limit for TDD depends on the type of application and on the operation conditions (reverse diode bias).

Large-area epitaxy of layered materials is one of the cornerstones for a successfulexploitation of van der Waals (vdW) materials in the semiconductorindustry. The formation of 60° twin stacking faults and 60° grain boundariesis of major concern for the defect-free epitaxial growth. Although strategiesto overcome the occurrence of these defects are being considered, morefundamental understanding on the origin of these defects is highly essential.This work focuses on understanding the formation of 60° twins in (quasi-)vdW epitaxy of 2D chalcogenides. Molecular beam epitaxy (MBE) experimentsreveal the striking difference in 60° twin occurrence between WSe2and Bi2Se3 in both quasi-vdW heteroepitaxy and vdW homoepitaxy. Densityfunctional theory (DFT) calculations link this difference to the interlayer vdWcoupling strength at the unit cell level. The stronger interlayer vdW coupling in Bi2Se3 unit cells compared to WSe2 unit cells is explained to resultin a reduced twin occurrence. Hence, such compounds show significantlymore promise for defect-free epitaxial integration. This interesting aspectof (quasi-)vdW epitaxy reveals that the strength of interlayer vdW couplingis key for workable 2D materials and opens perspectives for other stronglycoupled vdW materials.

Layered materials held together by weak van der Waals (vdW) interactions are a promising class of materials in the field of nanotechnology. Besides the potential for single layers, stacking of various vdW layers becomes even more promising since unique properties can hence be precisely engineered. The synthesis of stacked vdW layers, however, remains to date, hardly understood. Therefore, in this work, the vdW epitaxy of transition metal dichalcogenides (TMDs) on single-crystalline TMD templates is investigated in depth. It is demonstrated that the role of lattice mismatch is insignificant. More importantly is the role of surface energy, calculated using density functional theory, which plays an essential role in the activation energy for adatom diffusion, hence nucleation density. This in turn correlates with defect density since the stacking sequence in vdW epitaxy is generally poorly controlled. Moreover, the vapor pressure of the transition metal is also found to correlate with adatom diffusion. Consequently, the proposed study enables important and new insight in the vdW epitaxy of multilayer 2D homo-/heterostructures. ispartof: ACS APPLIED MATERIALS & INTERFACES vol:12 issue:24 pages:27508-27517 ispartof: location:United States status: published

Barium titanate (BaTiO3 or BTO) is a perovskite structure material with interesting intrinsic properties, such as spontaneous ferroelectricity or electro-optical behavior, which strongly depend on thin film crystallinity. For such functional oxide systems, the pulsed-laser deposition (PLD) approach is one promising growth technique due to its precise stoichiometry control of the metals composing the perovskite crystal and higher oxygen environment compared to the classically used molecular beam epitaxy (MBE) approach. In this article, we demonstrate a BTO epitaxial layer by PLD onto an Si(001) substrate thanks to a thin pseudomorphic SrTiO3 buffer layer grown by MBE. In our study, the various investigated PLD parameters show strong impacts on the BTO polarization orientation. Hence, adjusting the growth conditions allows control of the polarization orientation, which is crucial for both electronic and optical applications. In addition, lattice parameter changes of BTO layers are investigated using x-ray diffraction and cross-sectional transmission electron microscopy, which evidenced a correlation between mismatch relaxation and oxygen growth pressure. Finally, with the analysis of BTO C– V curves, the polarization direction transition is demonstrated electrically. ispartof: Journal Of Applied Physics vol:128 issue:10 pages:104104-104104 status: published

The increasing scientific and industry interest in 2D MX

© 2018 Elsevier B.V. Quantum Dots (QDs) are considered as an efficient building block of many optoelectronic applications, such as semiconductor laser, photodetector, whereby their physical dimension is the key parameter to be controlled. In this work, we have studied experimentally the growth of InAs QDs on InP(0 0 1) substrate by MOVPE and established a theoretical model explaining the observed epitaxial behaviour. In variance with the classical Stranski-Krastanov growth, we show that during the growth there is an intermediate stage whereby although first large 3D islands are formed, an increased density of small QDs is formed concurrent with the shrinkage of the large 3D islands. As a result, the growth can be divided into three regimes: 2D layer growth, large 3D islands growth and QDs growth. To explain this evolution, a thermodynamic model has been developed accounting for the process driven by surface energy, elastic relaxation energy and inter-island interaction energy. It will be shown that the balance between the surface energy and the elastic relaxation energy provides the transition from 2D layer to large 3D islands (around at 3 ML of InAs growth). This model also supports the energetically favourable truncated pyramidal shape for large 3D islands and the spherical cap shape for QDs. We show in this paper that a balance between surface energy, elastic relaxation energy and inter-island elastic interaction explains the volume shrinkage of the early large 3D islands towards the formation of small QDs in high density. ispartof: JOURNAL OF CRYSTAL GROWTH vol:509 pages:133-140 status: published

The three-dimensional carrier confinement in Quantum Dots (QDs) is the key to achieve superior properties (electronic and optical) compared to the Quantum Well (QWL) for optoelectronic applications, such as semiconductor lasers, photodiodes. After the growth of QDs, the encapsulation is the next crucial step to confine carriers in QDs and achieve the targeted wavelength emission. In this work, we have studied the InP capping of Stranski-Krastanov (S-K) grown InAs QDs on InP(0 0 1) substrate by MOVPE. During the encapsulation, the P/As exchange is a vital process which either transforms the QDs into a 2D layer or reduces QDs’ dimensions. This study shows that a control of Phosphorous concentration on the surface during InP capping facilitates to obtain the expected QDs dimension for 1550 nm wavelength. The emitted photoluminescence peak shifts following the preserved average QDs’ dimensions. By combining simulation with optical response we have proved the Phosphorous incorporation into the InAs structure (QDs or 2D layer) during the encapsulation step. As expected, the carrier lifetime reveals the superior quality of the preserved QDs in InP barrier compared to the 2D layer. Finally, the reduction of the non-radiative recombination sources, e.g. dangling bonds, by passivation treatment demonstrates a further increment in carrier lifetime.

Several approaches for growing III–V lasers on silicon were recently demonstrated. Most are not compatible with further integration, however, and rely on thick buffer layers and require special substrates. Recently, we demonstrated a novel approach for growing high quality InP without buffer on standard 001-silicon substrates using a selective growth process compatible with integration. Here we show high quality InGaAs layers can be grown on these InP-templates. High-resolution TEM analysis shows these layers are free of optically active defects. Contrary to InP, the InGaAs material exhibits strong photoluminescence for wavelengths relevant for integration with silicon photonics integrated circuits. Distributed feedback lasers were defined by etching a first order grating in the top surface of the device. Clear laser operation at a single wavelength with strong suppression of side modes was demonstrated. Compared to the previously demonstrated InP lasers 65% threshold reduction is observed. Demonstration ...

Two-dimensional transition metal dichalcogenide (TMD) semiconductors have risen as an important material class for novel nanoelectronic applications. Molybdenum disulfide (MoS2) is the most representative TMD compound due to its superior stability and attractive properties for (opto-) electronic devices. However, the synthesis of single-crystalline and functional MoS2 across large-area substrates remains crucial for its successful integration in semiconductor industry platforms. Therefore, this work focuses on the study of MoS2 epitaxy via two well-established industry-compatible synthesis methods, promising for the large-area and single-crystalline integration of van der Waals (vdW) materials. These methods are molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) and have studied MoS2 quasi-vdW heteroepitaxy on reconstructed sapphire substrates and MoS2 vdW homoepitaxy on exfoliated MoS2 flakes. By examining the MoS2 structural properties using diffraction and spectroscopy techniques, the epitaxial relation and crystal quality are assessed, which reveals insights into the prevalence of inter- and intragrain defects such as grain boundaries and sulfur vacancies. The MBE method yields superior epitaxial MoS2 registry on both sapphire and MoS2 surfaces as compared to MOVPE, although inferior defectivity arises from the typical lower MBE growth temperature and chalcogen partial pressure. Moreover, both synthesis methods generate high densities of twinned MoS2 grain boundaries, which hamper defect-free integration. As a result, this challenging integration might become an important bottleneck for industrial TMD-based applications with a low tolerance for material defects.

ispartof: 2D MATERIALS vol:7 issue:2 status: published

Stranski-Krastanow (S-K) grown self-assembled quantum dots (QDs) are considered as an efficient active layer for many optoelectronic applications, such as semiconductor laser, photodetector, due to the possibility to confine carriers in three dimensions. Towards the device application, the subsequent growth of an encapsulation layer is a key step to obtain the desired QDs-based heterostructures. In this work, we have studied step-by-step the encapsulation process of S-K grown InAs QDs/InP(0 0 1) by InAlGaAs (lattice matched to InP) in MOVPE. A detailed investigation with Electron Channeling Contrast Imaging (ECCI) and cross-sectional Transmission Electron Microscopy (TEM), indicated that after the InAlGaAs capping the partially relaxed, dome shaped InAs QDs are transformed into fully biaxially strained, truncated pyramids however without introducing any defects in the heterostructure. The study also presents the important role of the capping layer thickness on the QDs photoluminescence efficiency. The gradual change of the surface morphology during the encapsulation process, has been investigated step-by-step in-depth by atomic force microscopy. The morphological changes can be explained by a capping model based on the localized growth rates. We show that two growth steps of Non-uniform capping, where growth rates are different from each other, result in the successful planarization of the InAlGaAs capping without forming any defect.

© 2018 Author(s). We study in this work the growth and fabrication of top-down highly doped n + InAs(Si)/p + GaSb(Si) Esaki tunneling diodes on (001) GaAs substrates. A careful investigation on the highly mismatched GaSb/GaAs growth is first conducted by means of Reflection High-Energy Electron Diffraction (RHEED), Atomic Force Microscopy (AFM), and X-Ray Diffraction (XRD) analyses. These results are expected to pave the way to methods for III-Sb buffer layer's integration with low threading dislocation (TD) densities. A comparison between AFM, XRD, defect revealing by chemical etching and transmission electron microscopy (TEM) is then presented to calculate the precise TD density and its influence on the device structure. In the last part, we report on first operating sub-30 nm III-V vertical NW tunneling devices on (001) commercial GaAs substrates. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:19 status: published

In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300 mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with L G = 60 nm have a peak transconductance of 1030 μS/μm with a SS SAT of 125 mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high- k interface. Nanowires with a diameter of 6 nm were demonstrated to show quantization induced immunity to D it resulting in a SS SAT as low as 66 mV/dec for 85 nm L G devices.

aalso at E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium Since the 45 nm CMOS node, high-k gate dielectrics and strain engineering go hand in hand to further boost the transistor performance. An example of a so-called global strain platform relies on a thin strained-silicon (sSi) layer on top of a strain-relaxed Si1-xGex buffer (SRB) (Fig. 1). In addition, replacing thermally grown SiO2 by a deposited dielectric opens the door for the implementation of so-called high-mobility channel materials (Ge – pMOS; InxGa1-xAs – nMOS;...), which can be grown hetero-epitaxially on a silicon substrate. Due to the lattice mismatch of most of these materials with silicon, strain relaxation will occur above a certain critical thickness, leading to the introduction of both misfit and threading dislocations (TDs). It is well-known that dislocations introduce a one-dimensional band of states in the band-gap and hence are electrically active [1],[2]. The aim of the present review is to address the impact of such extended defects on the electrical performance of simple devices (p-n junctions, MOSFETs,...) for various high-mobility materials. A first example which will be discussed is the impact of TDs on the current-voltage (I-V) characteristics of p-n junctions fabricated in sSi and relaxed-Ge-on-Si substrates. As can be derived from Fig. 1, the depletion region mainly extends in the SiGe SRB, so that the electrical activity of the dislocations in this layer will be probed. It is clear from Fig. 2 that the reverse current IR of the diodes more or less proportionally increases with the density of TDs [3]. The same applies for the recombination and generation lifetime. Similar studies have been carried out for p-n junctions fabricated in a Si0.2Ge0.8 SRB and in relaxed Ge-on-Si epi layers. Summarizing all these results in Fig. 3, one can observe that the area leakage current density increases proportionally with the density of TDs and exponentially with the Ge content [4]. The latter can be explained by considering the impact on the band gap, yielding an exponential increase of the intrinsic carrier density. Comparing with Fig. 3b, it is clear that there exists a trade-off between leakage current density and epi layer thickness: thinner relaxed Ge layers on silicon will have a higher equilibrium TD density [5] and, hence, leakage current. However, considering a typical SRAM cell design, it can be concluded that for typical TDD values of 107-108 cm-2, the contribution to the off-state leakage is negligible compared with the contribution of the perimeter. A second example investigates the impact of anti-phase boundaries (APBs) on the reverse current of p-n junctions fabricated in GaAs (Fig. 4a) will be discussed. As can be derived from Fig. 4b, there is a modest increase of IRbetween on-axis junctions with a high APB density and off-axis diodes. Overall, it has been concluded that APBs are not so efficient leakage generators in GaAs. Finally, the impact of TDs on other device parameters, like the mobility or the threshold voltage of a MOSFET will be discussed. References [1] W. Schröter and H. Cerva, Solid State Phenomen., 85-86, p. 67 (2002). [2] E. Simoen et al., J. Electrochem. Soc., 158, p. R27 (2011). [3] G. Eneman et al., Appl. Phys. Lett., 87, p. 192112 (2005). [4] E. Simoen et al., J. Electrochem. Soc., 157, p. R1 (2010). [5] G. Wang et al., Appl. Phys. Lett., 94, p. 102115-1 (2009). Figure 1

We study in this paper the epitaxial growth and electrical characterization of an n+In 0.5 Ga 0.5 As/p+GaAs 0.5 Sb 0.5 Esaki diode lattice matched to (001)-oriented InP substrate. First, the effects of molecular beam epitaxy growth temperature and group-V growth rates on the GaAs x Sb 1− x composition are characterized by means of X-ray diffraction (XRD). It is found that GaAs x Sb 1− x lattice constant is mainly determined by the Sb 4 incorporation rather than the As 4 one. After optimization, high quality In 0.54 Ga 0.46 As(Si)/GaAs 0.52 Sb 0.48 (Be) heterostructure is confirmed by XRD, Transmission electron microscope (TEM) and Secondary Ion Mass Spectroscopy (SIMS) profiles meeting requirements for sub-60 mV/dec operating devices. Esaki tunnel diodes are then fabricated to be used as a prediction of Band-To-Band Tunneling (BTBT) for Tunnel Field-Effect transistors (TFETs). The results are compared to previously reported n+/p+In 0.5 Ga 0.5 As homojunction diodes, showing a ×60 factor improvement of BTBT current density for the same electric field with an excellent average Peak-to-Valley Current Ratio (PVCR) of 14.

The ongoing study of {111} planar defects (PDs) in III–V nanowires (NWs) entails a fast and quantitative characterization method beyond transmission electron microscopy (TEM). We report here a simple and reliable method to calculate the PD frequency in InAs NWs using a lab X-ray diffractometer. The fact that the PD distribution is location independent and irrelevant to the NWs diameter in catalyst-free InAs NWs epitaxy makes PD frequency global calculation possible. We demonstrated that the PDs follow a geometric distribution in NWs. As a consequence, applying a 1D disordered layers diffraction model, we relate the diffraction peak angle directly to the PD frequency. The calculated PD frequency values are in good agreement with that extracted from high resolution TEM analysis. As an example, we applied this method to study the influence of growth temperature on PD frequencies in the frame of a 2D nucleation model.

Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. Monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties. Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy. We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.

Extracting plasmon-induced hot carriers over a metal-semiconductor Schottky barrier enables photodetection below the semiconductor bandgap energy. However, interfacial carrier recombination hinders the efficiency and stability of this process, severely limiting its implementation in telecommunication. This study proposes and demonstrates the use of epitaxially grown lattice-matched SrTiO3 for interfacial passivation of silicon-based plasmonic Schottky devices. The devices are activated by an electrical soft-breakdown of the interfacial SrTiO3 layer, resulting in reproducible rectified Schottky characteristics. The transition to a low resistance state of the SrTiO3 layer boosts the extraction efficiency of hot holes upon resonant plasmonic excitation, giving rise to a two orders of magnitude higher photocurrent compared to devices with a native oxide layer. Photoresponse, tunability, and barrier height studies under reverse biases as high as 100 V present superior stability with the incorporation of the SrTiO3 layer. The investigation paves the way toward plasmon-induced photodetection for practical applications including those under challenging operating conditions.

This chapter deals with the monolithic integration of InGaAs semiconductor on (001)-oriented Si substrate. This starts with a brief introduction to III-V semiconductor epitaxy, the effect of strain, and the relaxation mechanisms. An overview of the different structural defects' families is also included in the section. In a second part, the two most popular III-V growth techniques that are molecular beam epitaxy and metal-organic vapor phase epitaxy are compared. The main challenge in the heterogeneous integration of InGaAs on Si resides in the material mismatch between both semiconductors that results in the high-density generation of crystalline defects. In this chapter, several options such as strain-relaxed buffers, wafer bonding, epitaxial lateral growth, and selective area growth have been considered to reduce the defect density in III-V compounds on Si, which will be reviewed. Finally, a rich literature completes the chapter.

New materials and device architectures will be needed to extend CMOS scaling.High mobility materials in the channel can boost the performance at scaled supply voltage.Ultimate reduction of power dissipation will require new concepts like Tunnel FET.Vertical devices and 3D stacking allow to further downscale the transistor dimensions. In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore's law to the sub-10nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS.

In this work, we report on the growth of pseudomorphic and highly doped InAs(Si)/GaSb(Si) heterostructures on p-type (0 0 1)-oriented GaSb substrate and the fabrication and characterization of n+/p+ Esaki tunneling diodes. We particularly study the influence of the Molecular Beam Epitaxy shutter sequences on the structural and electrical characteristics of InAs(Si)/GaSb(Si) Esaki diodes structures. We use real time Reflection High Electron Diffraction analysis to monitor different interface stoichiometry at the tunneling interface. With Atomic Force Microscopy, X-ray diffraction and Transmission Electron Microscopy analyses, we demonstrate that an “InSb-like” interface leads to a sharp and defect-free interface exhibiting high quality InAs(Si) crystal growth contrary to the “GaAs-like” one. We then prove by means of Secondary Ion Mass Spectroscopy profiles that Si-diffusion at the interface allows the growth of highly Si-doped InAs/GaSb diodes without any III-V material deterioration. Finally, simulations are conducted to explain our electrical results where a high Band to Band Tunneling (BTBT) peak current density of Jp = 8 mA/μm2 is achieved.

Themechanism of widely observed intermixing of wurtzite and zinc-blende crystal structures in InAs nanowire (NW) grown by selective area epitaxy (SAE) is studied. We demonstrate that the crystal structure in InAs NW grown by SAE can be controlled using basic growth parameters, and wurtzitelike InAs NWs are achieved.We link the polytypic InAs NWs SAE to the reconstruction of the growth front (111)B surface. Surface reconstruction study of InAs (111) substrate and the following homoepitaxy experiment suggest that (111) planar defect nucleation is related to the (1 × 1) reconstruction of InAs (111)B surface. In order to reveal it more clearly, a model is presented to correlate growth temperature and arsenic partial pressure with InAs NW crystal structure. This model considers the transition between (1 × 1) and (2 × 2) surface reconstructions in the frame of adatom atoms adsorption/desorption, and the polytypism is thus linked to reconstruction quantitatively. The experimental data fit well with the model, which highly suggests that surface reconstruction plays an important role in the polytypism phenomenon in InAs NWs SAE.https://doi.org/10.1103/PhysRevMaterials.1.074603

In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

In this presentation we will report on our recent work on new materials that can be monolithically integrated on high-index contrast silicon or silicon nitride photonic ICs to enhance their functionality. This includes graphene and other 2D-materials for realizing compact electro-absorption modulators and non-linear devices, ferroelectric materials for realizing phase modulators and adiabatic couplers for realizing bistable switches.

The low-frequency noise is studied in planar InGaAs channel nMOSFETs, with Al2O3 gate dielectric in combination with different pre- and post-gate treatments, namely, pre-gate TMA exposure or post-gate Forming Gas Annealing (FGA). It is shown that the oxide trap density is reasonably uniform in the gate stack between 1 and 2 nm from the interface, whereby a FGA yields a lower noise power spectral density compared with the TMA or untreated devices.

The relationship between the Threading Dislocation Density (TDD), the generation (τg) and recombination lifetime (τr) in relaxed n-type In.53Ga.47As is investigated for a series of p+n junction diodes, containing an TDD ranging from 105 to 1010 cm-2. The TDs are generated intentionally by lattice-misfit growth on Semi-Insulating (SI) InP and GaAs substrates. The lifetimes have been extracted from diode Current-Voltage (I-V) and Photoluminescence (PL) analysis showing that TDDs affect their values above a density of about 1×107 cm-2 (τg,E~0) and about 1×108 cm-2 (τr and τPL), which can be well-explained by the charged dislocation cylinder model. In addition, a detailed comparison between the results from Deep Level Transient Spectroscopy (DLTS) and from the diode characterization is performed, showing that the responsible G/R center shifts toward mid-gap in In.53Ga.47As and transfers from a native point defect (PD1) to a TD (E2/H1). Finally, the classical concept of generation lifetime and recombination lifetime in terms of dislocations is discussed based on the results.

The increasing scientific and industry interest in 2D MX2 materials within the field of nanotechnology has made the single crystalline integration of large area van der Waals (vdW) layers on commercial substrates an important topic. The c-plane oriented (3D crystal) sapphire surface is believed to be an interesting substrate candidate for this challenging 2D/3D integration. Despite the many attempts that have been made, the yet incomplete understanding of vdW epitaxy still results in synthetic material that shows a crystallinity far too low compared to natural crystals that can be exfoliated onto commercial substrates. Thanks to its atomic control and in situ analysis possibilities, molecular beam epitaxy (MBE) offers a potential solution and an appropriate method to enable a more in-depth understanding of this peculiar 2D/3D hetero-epitaxy. Here, we report on how various sapphire surface reconstructions, that are obtained by thermal annealing of the as-received substrates, influence the vdW epitaxy of the MBE-grown WSe2 monolayers (MLs). The surface chemistry and the interatomic arrangement of the reconstructed sapphire surfaces are shown to control the preferential in-plane epitaxial alignment of the stoichiometric WSe2 crystals. In addition, it is demonstrated that the reconstructions also affect the in-plane lattice parameter and thus the in-plane strain of the 2D vdW-bonded MLs. Hence, the results obtained in this work shine more light on the peculiar concept of vdW epitaxy, especially relevant for 2D materials integration on large-scale 3D crystal commercial substrates.

The electrical activity of a defect in a semiconductor material is usually expressed in terms of the Shockley-Read-Hall (SRH) theory which provides an expression for the generation or recombination lifetime. Along the same lines, one can calculate the leakage current generated by a single defect in the depletion region of a junction, as shown in Fig. 1 [1]. It is clear that for III-V based ternary alloys, like the InxGa1-xAs system, the generation current depends proportionally on the intrinsic carrier concentration ni (see equation in Fig. 1). However, equally important is also the variation of the defect energy level ET as a function of the In content x: for ET pinned to the intrinsic Fermi level Ei(x), the leakage current will follow ni. On the other hand, when ET is pinned to either the valence or conduction band, the leakage current will decrease exponentially with the difference |ET-Ei| [2]. It is thus important to derive the variation of ET with alloy composition x for a certain type of defect and to establish what could be consideredas a kind of Vegard’s law for specific deep levels. In addition, when integrating III-V compounds on a silicon CMOS platform, extended defects will be inevitably introduced [3]; for a sufficiently high density, they will govern the reverse current [3,4]. It is thus of vital importance to study the electrical parameters of extended defects in III-V-on-silicon materials and their evolution with composition x. The aim of the this work is to review what is known about the electrical activity of extended defects in InxGa1-xAs-based hetero-epitaxial layers. Results will be described about a combined p-n diode current-voltage (I-V) and lifetime analysis on a set of nearly strain-free layers where x=0.53 with varying densities of extended defects [5]. Based on this, it is demonstrated that for an extended defect density exceeding ~2×107 cm-2 the SRH lifetime becomes dominated by a near mid-gap trap level, associated with them. A detailed Deep-Level Transient Spectroscopy (DLTS) analysis provides further information about the electrical activity of these extended defects and confirms the presence of a dominant electron trap. The corresponding activation energy is represented in Fig. 2 versus x and compared with available literature data. In addition, it is shown that this deep level indeed belongs to an extended defect, based on the electron capture behavior, varying approximately logarithmically with the capture time [4]. Moreover, it can be shown that the electron traps belong to a one-dimensional band-of-states, associated with a ‘perfect’ extended defect. According to Fig. 2, this level appears to follow approximately Ei(x), so that it will dominate the leakage current of a p-n junction over a wide composition range, at least up to 0.53, when present in a sufficient density. Moreover, the defects will become more efficient leakage centers for increasing x. Finally, the implications of the band-like nature of the energy states of extended defects on the carrier generation/recombination will be discussed. [1] J. Vanhellemont and E. Simoen, J. Electrochem. Soc, 154, H572 (2007). [2] E. Simoen, J. Lauwaert and H. Vrielinck, Semiconductors and Semimetals, Eds. L. Romano, V. Privitera and C. Jagadish, 91, pp. 205-250, Elsevier 2015. [3] E. Simoen, “Impact of defects on the performance of high-mobility semiconductor devices”, In: High Mobility Materials for CMOS Applications, Ed. N. Collaert, Elsevier, Ch. 5, July 2018. [4] C. Claeys et al., ECS J. Solid State Sci. and Technol., 5, P3149 (2016). [5] P.-C. Hsu et al., J. Appl. Phys., 124, 165707 (2018). Figure 1

The observation and interpretation of Frank stacking faults, Shockley stacking faults, Lomer dislocations, and 60 degrees misfit dislocations, which have similar line shapes in the (001) In0.53Ga0.47As crystalline surface, are performed with the electron channeling contrast imaging (ECCI) technique. To minimize the backscattered electron (BSE) contrast that resulted from the surface morphology, a relatively flat region is first selected and compared with an atomic force microscopy (AFM) image and then, subsequently, examining ECCI with transmission electron microscopy (TEM)-like invisibility criteria. By orthogonally choosing the diffraction vector g between (220) and (2-20), misfit dislocations seem to be always visible but partially faint in the g parallel to the line direction on the surface. With respect to the image contrast, Frank stacking faults and Lomer dislocations are likely to be completely invisible for parallel g. The criteria are further confirmed by cross-sectional TEM analysis, which shows a preferred homogeneous surface nucleation.

In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.In this work, the epitaxy of SrTiO3 and BaTiO3 perovskites on the (001)-oriented silicon substrate by molecular beam epitaxy is investigated. The heterostructures are studied by means of various structural and electrical characterization techniques. In this study especially, the authors reveal experimentally by nanobeam electron diffraction analysis the critical thickness prior relaxation of BaTiO3 grown on an SrTiO3/Si pseudosubstrate. They also propose to use a strain mediated superlattice composed of stacked [BaTiO3/SrTiO3] bilayers to prevent misfit dislocation formation. Using this approach, they could demonstrate high quality and dislocation free BaTiO3 ferroelectric layers integrated on silicon as confirmed by piezo-force microscopy techniques.

The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.

On-chip optical interconnects still miss a high-performance laser monolithically integrated on silicon. Here, we demonstrate a silicon-integrated InP nanolaser that operates at room temperature with a low threshold of 1.69 pJ and a large spontaneous emission factor of 0.04. An epitaxial scheme to grow relatively thick InP nanowires on (001) silicon is developed. The zincblende/wurtzite crystal phase polytypism and the formed type II heterostructures are found to promote lasing over a wide wavelength range.

Deep levels associated with extended and point defects in MOS capacitors fabricated on unintentionally doped GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep Level Transient Spectroscopy (DLTS). A 9nm layer of Al2O3 is deposited as high-k gate dielectric by Molecular Beam Epitaxy. The trap kinetics and origin of defect states is discussed. Also, it is shown that the dislocation cores in relaxed p-Ge are associated with band-like donor-like states in the lower half of forbidden band gap, and act as carrier trapping and recombination centers. In addition, slow and fast oxide interface traps are observed.