163 results on '"Chamberlain, S.G."'
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2. Compact Spice Modeling and Design Optimization of Low Leakage a-Si:H TFTs for Large-Area Imaging Systems
3. High performance a-Si:H thin film transistors based on aluminum gate metallization
4. Capturing images at 1000 feet per minute with TDI
5. The IEEE Oceanic Engineering Society: From National to Global, 1968-2009.
6. Fabrication of a-Si:H Tfts at 120°C on Flexible Polyimide Substrates
7. Thick-layered etched-contact amorphous silicon transistors
8. A comparison of the performance and reliability of wet-etched and dry-etched a-Si:H TFTs
9. Effect of Nh3/SiH4 Gas Ratios of Top Nitride Layer on Stability and Leakage in a-Si:H Thin Film Transistors
10. Process Integration of A-Si:H Schottky Diode and thin Film Transistor for Low-Energy X-Ray Imaging Applications
11. Improvement of the reliability of amorphous silicon transistors by conduction-band tail width reduction
12. The source-gated amorphous silicon photo-transistor
13. A realistic trap distribution model for numerical simulation of amorphous silicon thin-film transistors and phototransistors
14. The effects of metal-n/sup +/ interface and space charge limited conduction on the performance of amorphous silicon thin-film transistors
15. Drain-induced barrier lowering in buried-channel MOSFET's
16. A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors
17. Theory and design methodology for an optimum single-phase CCD
18. a-Si:H Schottky diode direct detection pixel for large area X-ray imaging.
19. Mega pixel CCD image sensor technology.
20. Nonuniform displacement of MOSFET channel pinchoff.
21. Three-dimensional simulation of VLSI MOSFET's: The three dimensional simulation program WATMOS.
22. Profiled silicon photodetector for improved blue color and visible wavelength quantum efficiency.
23. High resolution tri-linear colour TDI CCD image sensor with programmable responsivity gain.
24. An analytical model for a-Si:H transistors based on TFT device characteristics.
25. Buried-channel MOSFET model for SPICE
26. Analytic and iterative transit-time models for VLSI MOSFETs in strong inversion
27. Transient analysis of electrical charge injection into charge-coupled devices.
28. Some general experimental studies on charge-coupled device circuits.
29. A novel wide dynamic range silicon photodetector and linear imaging array.
30. Nonuniform displacement of MOSFET channel pinchoff.
31. Three-dimensional simulation of VLSI MOSFET's: The three-dimensional simulation program WATMOS.
32. Modeling and measurement of minority-carrier lifetime versus doping in diffused layers of n+-p silicon diodes.
33. Two-dimensional simulation of a high-voltage p-i-n diode with overhanging metallization.
34. Limitations of multilevel storage in charge-coupled devices.
35. Modeling and experimental simulation of the low-frequency transfer inefficiency in bucket-brigade devices.
36. Spectral response limitation mechanisms of a shallow junction n+-p photodiode.
37. MTF simulation including transmittance effects and experimental results of charge-coupled imagers.
38. A multiple-gate CCD-photodiode sensor element for imaging arrays.
39. Short-channel effects on the input stage of surface-channel CCD's.
40. A study of the effect of peripheral injection in bipolar transistors using simplified computer analysis.
41. CHORD: a modular semiconductor device simulation development tool incorporating external network models.
42. Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications.
43. A calibrated model for the subthreshold operation of a short channel MOSFET including surface states.
44. Experimental confirmation of an analytical model for charge transfer in charge-coupled devices.
45. Potential and electron distribution model for the buried-channel MOSFET.
46. Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations.
47. Two-dimensional computer simulation of the breakdown characteristics of a multi-element avalanche photodiode array.
48. Design of low-noise bipolar transimpedance preamplifiers for optical receiver.
49. A CMOS model for computer-aided circuit analysis and design.
50. A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits.
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