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Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations.

Authors :
Chamberlain, S.G.
Ramanan, S.
Source :
IEEE Transactions on Electron Devices; 1986, Vol. 33 Issue 11, p1745-1753, 9p
Publication Year :
1986

Details

Language :
English
ISSN :
00189383
Volume :
33
Issue :
11
Database :
Complementary Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
93115905
Full Text :
https://doi.org/10.1109/T-ED.1986.22737