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The purpose of pellicles is to protect reticles from particle contamination, thus reducing the number of defects and increasing yield. In this paper we show how recent progress in pellicle technology has succeeded in solving the main challenges in imaging with EUV pellicles. We demonstrate this using the recent results of imaging tests in scanner, EUV reflectivity measurements, and lifetime testing. EUV light reflectivity of pellicles is one of the effects that have negatively impacted imaging with pellicles in the past. Light reflected from pellicles leads to the overexposure of neighboring fields in the corners and edges. Tests with pellicles produced using a new process show EUV reflectivity within specification of 0.04%, and measured impact on critical dimension in the corners below 0.15nm for multiple pellicles. Lifetime performance was tested by exposing up to 3000 wafers with a pellicle while periodically assessing the stability of imaging metrics. The lithometrics studies include: critical dimension (CD) and critical dimension uniformity (CDU), and contrast (via line width roughness). DoseMapper, which is an EUV scanner application developed to improve CDU, was applied during the lifetime test. Here we show that it can successfully reduce the pellicle-induced CDU and CDU over lifetime (previously shown to be dominated by pellicle EUV transmission drift). Our results using DoseMapper show that whilst intrafield CDU 3sigma increases over lifetime, it stays comfortably within the 1.1nm NXE3400 ATP specification using DoseMapper.

This chapter provides an overview of contamination that can be encountered during semiconductor device manufacturing. Contamination can have a detrimental impact on yield and reliability, but also on process control. In the conventional classification scheme, a distinction is made between particle contamination, metallic contamination, and airborne molecular contamination. For each of these contaminants, a brief overview is given of the sources of contamination and the mechanisms by which the contamination is deposited on the substrate surface. Also general properties and possible effects of the contamination are discussed. In addition, possible detrimental effects of contaminant removal and cleaning are reviewed.

Exposure of TSVs from the backside in 3D-SIC is a multistep process [1-. Two steps in this process flow (thinning module) are potentially a high risk for particle contamination: wafer edge trimming and wafer thinning by grinding.

Particles and scratches are most wanted defects to be minimized in CMP processes. The root causes for them are mostly consumables related such as pad, slurry and diamond conditioning. The evaluation of additives in slurry is neglected in terms of their defect generation on wafer. The adhesion force can be measured between particle and wafer surface in given chemistry to select the additive which causes least particle contamination in both slurry and cleaning solutions. Also, the scratch detection and analysis are very time consuming and require advanced methodology even in wafer production facility. The lab scale scratch detection method was developed to study the effect of slurry and conditioning on wafer during CMP. In this presentation, we report the utilization of particle adhesion force on CMP process development and the detection of scratches on oxide wafer. The effect of slurry, pad and diamond conditioner on scratch formation was investigated with their classification

The effects of pumping method on wafer cleaning were investigated. Two types of pump such as diaphragms and centrifugal were used for circulation and supply of DI water for wafer cleaning in both wet bath and single wafer tool. The cleaning studies show that the pumping methods have a great influence on cleaning performance. The experimental investigations reveal that the number of added particles on the wafer during wafer cleaning is much lesser in MLC pump (non-pulsation flow) than the both diaphragm pumps (pulsation flow).

The influence of environmental particle contamination on offline measured defects and manufacturing yield in integrated circuits is discussed. One of the sources of particle contamination is ultra pure water used in different production tools at different stages of processing. Particle count data measured in ultra pure water is compared with the offline defects caused by process tools and the relation has been statistically confirmed. Particle count data is also compared with the defect density of large size products. An impact of particle contamination on yield of 4–6% has been found. In this study, fundamentals are provided to define the meaningful specifications of ultra pure water for wafer fabrication.

In many process steps of integrated circuits (IC’s) fabrication, silicon wafers are coming in contact with process liquids such as ultra pure water (UPW) and aqueous and non-aqueous chemical mixtures. During these process steps, liquid-borne particle contamination can deposit on the wafer surface. Particle contamination from UPW is an important factor influencing random yield loss of IC’s [ ]. A number of yield models are used to predict yields including Poisson, Murphy, Seeds, and negative binomial models [ , ]. However, these models are based on the assumption that particles are randomly deposited on the wafer surface [ ].

The increasing complexity of semiconductor devices imposes challenging requirements on particle contamination and surface damage. To meet these requirements novel surface-cleaning processes are evaluated, which combine physical energy with organic solvents. In this work, the performance of megasonic cleaning with deionized water (DIW) and N-methylpyrrolidone (NMP) was evaluated in terms of particle removal efficiency (PRE) and damage analysis. The goal was to define an optimum process window where the PRE was maximum and the damage was minimum. Particle removal and damage analysis were performed on unpatterned silicon wafers and with patterned polysilicon lines, respectively, under identical sonic power and process parameters. A comparison between these two solvents reveals that at low sonic power the particle-cleaning performances in DIW and NMP are similar. At high sonic power, in both solvents a detailed analysis of the PRE and damage indicates a non-homogeneous trend over the surface of the wafer. Mor...

The purpose of this study is to investigate the effects of slurry pH on the adhesion and removal of silica and ceria abrasive particles on the poly Si, TEOS, SiN and SAC (self aligned memory cell contact) and STI (shallow trench isolation) patterned wafer surfaces. The adhesion force of silica and ceria particles were theoretically and experimentally investigated in STI and poly Si CMP process. A stronger adhesion force was observed for silica particles on the poly Si wafer in acidic rather than in alkaline solutions. The adhesion force of ceria particle was lower than that of silica in investigated pH ranges. STI patterned wafer showed lower adhesion force than SAC patterned wafer. Lower adhesion force between particles and surface resulted in a lower level of particle contamination.

Control of chemical contaminant has become of great importance in addition to particle contamination in a clean room for manufacturing semiconductors, liquid crystal device and other electronics devices. In particular, acid gases, base gases, hydrocarbon gases, boron and phosphor could damage electrical properties of these devices. Therefore, the reduction of contaminant concentration in clean room air is required. In this paper, constitute materials for a clean room newly developed as countermeasure for chemical contamination are introduced. Then, their analysis and evaluation methods for chemical contamination are also described.

This article presents a study of particle formation during vacuum pump down and methods that can be incorporated to protect critical surfaces (like semiconductor wafers or masks) from those particles. Particle formation during pump down was reexamined with temperature measurements. Particles were intentionally produced with hard pump down for studying protection schemes. For the first step, a face-down approach for a critical surface was used to investigate the effect of protection from particle contamination. It was very effective to hold a critical surface face down for protection with the use of high gravitational settling velocity in vacuum environment. However, the face down approach did not sufficiently protect the critical surface. For the second step, a bottom protective plate was introduced below the critical surface to improve the protection efficiency. The bottom plate played a great role in protection of the critical surface with preventing particle formation near the critical surface by keeping the surrounding gas temperature high enough to avoid particle formation as well as with potential blocking of incoming particles toward the critical surface. Higher gas temperature intrinsically avoids formation of residue particles by the condensation process during pump down.

Introduction The preparation of surfaces free of particle contamination is one of the crucial prerequisites for a further increase in the integration density of ICs and for the progress in nanotechnology. Therefore the removal of sub-micron sized particles from silicon wafers is of great interest. For this purpose a variety of cleaning methods is currently under investigation. In semiconductor industry an ideal cleaning technique should be capable of removing particles with a diameter considerably below 100 nm, while a damage to the substrate has to be strictly avoided. Furthermore the process should be environmentally friendly and cost-effective. A promising approach which meets these requirements is called Laser Cleaning. So far two major approaches can be distinguished. The first one is called Dry Laser Cleaning (DLC), where the surface to be cleaned is simply irradiated by a short laser pulse [1,2,3]. In Steam Laser Cleaning (SLC) a thin layer of a liquid energy transfer medium is deposited on the surface prior to the laser pulse [1,2,4,5]. In this paper we will present a short overview of these techniques followed by some of our recent results. The emphasis lies on the underlying mechanisms and an industrial applicability of both cleaning methods.

The adhesion force and removal of alumina particles on Cu, Ta, TEOS, SILKTM, Aurora and FSG wafer surfaces were experimentally and theoretically investigated in slurry solutions of different pHs. These wafer surfaces showed negative zeta potentials in the investigated pH ranges with exception of FSG and Ta. However, the zeta potentials of FSG surface drastically decreased with increasing pH. The lowest adhesion force and smallest number of alumina particles were measured between alumina particle and FSG surface in a slurry solution of pH 11. Alkaline slurry was much more desirable in controlling the level of particle contamination during Cu CMP. The pH of the slurry and zeta potentials of the surfaces played important roles in controlling the interaction force.

The importance of controlling airborne particle contamination in clean rooms and wafer environment is well-known and much effort has been devoted to keep the particle contamination from wafer environment. Table 1 shows particle detection limit on wafer suggested by ITRS 2012 that is desirable in the future flash half pitch size. It indicates wide diameter range of airborne particles, from the size smaller than 100 nm, is required to be detected and controlled with the device pattern size becoming smaller and smaller. This study is focused on particle contamination from clean rooms into wafer environment. Front opening unified pods (FOUP) and equipment front end modules (EFEM) were taken as an example of wafer environment. Furthermore, the possible future work on keeping the contamination from wafer environment was discussed.

The minimization of particle contamination during wet processing of Si wafers, such as from particles in solutions with surfactants, was studied. It was demonstrated that particle deposition on wafer surfaces in solutions is determined by an attractive or a repulsive electrostatic force through the zeta potentials of particles and substrates. In practice, wafer surfaces consist of materials such as Si, poly-Si, SiO 2 , Si 3 Na 4 , Al-alloy, and photoresist, and all these materials exhibit different zeta potentials in wet chemical solutions. In solutions with a pH

EUV lithography is the most promising candidate for semi conductor device manufacturing of 1x nm half pitch and beyond. For the practical use, EUV mask with a thin absorber could be adopte d because of less shadowing effect. EUV reflectivity from the thin absorber is about 1~3%. It would cause CD change on wafer especially at the exposure field edge due to the leakage of the EUV light from neighboring exposure shots. 1 To avoid this phenomenon, light shield black border is needed at the edge of pattern area on mask. Stacked absorber type and ML-etched type of light shield black border have been proposed in the past. 2. The most important things for these black borders are that there is no reflection of EUV light and no defect which affects pattern CD on wafer. ML-etched black border is considered to be applied for early practical use from a viewpoint of manufacturability. Because CD degradation and defect increase might happen due to 2 nd litho and etch process on its main pattern area in manufacturing process of stacked absorber type. In this paper, we will show several evaluation results rega rding ML-etched black border we have developed. It has a good light shield performance for EUV and low DUV light reflection. Defect inspection in black border area can be performed successfully by three kinds of inspection tools. As a result, most of the defects seemed not to be printable to wafer. We also evaluated CD change, flat ness change linked to mask IP shift and particle contamination on main pattern area. What it comes down to is that there is no show-stopper for ML-etched BB process for now. Keywords: EUV lithography, mask, absorber, multilayer, light-shield, black border, reflectivity, OoB, image placement

In conventional 200 mm wafer processing, backside defects are not considered to be of much concern because they are obscured by wafer backside topography. However, in current 300 mm wafer processing where both sides of a wafer are polished, backside defects require more consideration. In the beginning, backside defect inspection examined particle contamination because particle contamination adversely influences the depth of field in lithography. Recently, metal contamination is of concern because backside metal contamination causes cross‐contamination in a process line, and backside metals easily transfer to the front surface. As the industry strives to yield more devices from the area around the wafer edge, edge exclusion requirements have also become more important. The current International Technology Roadmap for Semiconductors [1] requires a 2 mm edge exclusion. Therefore, metal contamination must be controlled to less than 2 mm from the edge because metal contamination easily diffuses in silicon wafers. To meet these current semiconductor processing requirements, newly developed zero edge exclusion TXRF (ZEE‐TXRF) and backside measurement TXRF (BAC‐TXRF) are effective metrology methods.

The concept of Extreme Ultra-Violet Lithography (EUVL) mask dual pods is proposed for use in both mask shipping and handling in exposure tools. The inner pod was specially designed to protect masks from particle contamination during shipping from mask houses to wafer factories. It can be installed in a load-lock chamber of exposure tools and evacuated while holding the mask inside. The inner pod upper cover is removed just before the mask is installed to a mask stage. Prototypes were manufactured and tested for shipping and for vacuum cycling. We counted particle adders through these actions with a detectable level of 54 nm and up. The adder count was close to zero, or we can say that the obtained result is within the noise level of our present evaluation environment. This indicates that the present concept is highly feasible for EUVL mask shipping and handling in exposure tools.

In the present manufacturing process of a silicon wafer, wafer edge finishing with loose abrasives is essential for preventing wafer breakage and particle contamination due to micro cracks. Loose-abrasive machining, however, has problems involving inefficiency and an unclean working environment. Therefore, fixed-abrasive machining such as film lapping has received attention as an alternative technology, but conventional lapping films have problems involving low finishing efficiency or low finished surface quality. In this study, agglomerative superfine silica abrasives are adopted in the lapping film to overcome these problems. The finishing experiments revealed that a high edge surface quality can be achieved with high efficiency.

The process performance of the Axcelis Technologies MC3, medium current implanter for 300 mm wafers, is reviewed. The MC3 is based on an evolutionary design approach. It uses proven beam transport, electrostatic scanning, beam parallelism, and energy purity schemes based on the successful 8250/sub HT/ design. Metals contamination, beam parallelism, energy purity, particles, and dose uniformity and repeatability are reviewed. The results show that metals contamination, parallelism, and particle contamination are better than those for the 8250/sub HT/. Energy purity, dose repeatability and uniformity are similar to the ones achieved with 8250/sub HT/.

Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by the geometry of the routing channels and the distribution of defect sizes. Since the wire spacing and width are usually fixed, and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts, and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Since the probability of failure is determined by the behavior of the wires averaged over the entire interconnect, the application of System Level Interconnect Prediction (SLIP) techniques is particularly appropriate. This paper presents a method for utilizing previously developed techniques for wire length estimation and layer assignment and applies them to the problem of cut and bridge functional yield estimation.

Due to mechanical and exposure considerations, NGL mask technology lacks the ability to use a pellicle to prevent mask contamination. The PLASMAX (Plasma Mechanical Activation and Extraction of Particle Contamination) process represents a technology, which acts as the functional replacement of a pellicle for the NGL mask. This dry environmentally benign cleaning technology can be directly integrated into the exposure system and serves as an in-situ creative mask cleaning process. Unlike other, more conventional cleaning methods, PLASMAX lifts surface particles from the mask, then suspends, traps and channels these particles down the vacuum port, thus preventing particle redeposition on the mask surface. Originally demonstrated on wafers, this plasma/mechanical cleaning technology has demonstrated its ability to remove particles from the surface of NGL masks such as SCALPEL (Scattering with Angular Limitation in Projection Electron Beam Lithography) masks. PLASMAX uses the combined action of a gentle plasma with simultaneous vibration to clean the mask. Unlike all other methods of mask cleaning, PLASMAX uses no water or hazardous acids, thus reducing the cost of each cleaning step and eliminating the environmental impact of today's aqueous cleaning technologies. Initial work with SCALPEL masks showed them to be highly stable and robust in the PLASMAX environment while yielding cleaning efficiencies of 90% removal of polyester particles 0.8 micron and larger. The PlASMAX technology was proven to be effective in removing particles from the patterned front side and strutted backside of the mask. This paper focuses on the ongoing development of PLASMAX to enhance the cleaning efficiency of SCALPEL masks down to 0.25-micron particles. In addition, the cleaning efficiency of various particle materials will be studied. Sandia National Laboratories is providing software model simulations of the PLASMAX technology to assist in the development effort.

In this paper, four major defects for metal etch process will be introduced and discussed. The defect sources related to chamber condition are identified as well. These defects are classified into four types: (1) flake type metal residue, induced by chamber polymer, (2) ball type particle, resulted from the chamber wall arcing during process, (3) on film particle, found during post-etch and photo resist strip processes, (4) metal broken, came from local arcing on wafer. All of these defects would result in metal line bridge and yield loss. In order to reduce the particle contamination, the paper proposes a protection method for chamber parts by using so called `linear' to cover most of chamber parts. The liner could adapt to chamber shape and clean easily. Experimental data shows that it can successfully reduce flake type metal residue, ball type particle. For the on film particle and metal broken, a new routine monitor method is also created.

The control of particle contamination is one of the main challenges on the way to higher integration of semiconductor devices. Although many of the production steps take place in a vacuum ambient, the behaviour of microcontaminants under vacuum conditions is not yet fully understood. Using laser-surface and air-borne particle detectors we have evaluated different venting and pumping procedures to gain quantitative information upon what is often called ‘soft venting’ and ‘soft pumping’. The results show that the number of air-borne particles in vacuum chambers can be kept well below cleanroom-class 10 after proper pumping and venting. The surface-particle-density increase, observed under these conditions, is below 10 −3 cm −2 for particles larger than 0.3 μm diameter for horizontal and vertical orientation of wafers.

In order to ensure high device performance and reliability in the next generation of ULSI, what is required of next-generation cleaning? First, the attainment of a high level of cleanliness which corresponds to the levels of miniaturization and high integration. This is the basic cleaning performance, but at levels even higher than have been required in the past. Precision cleaning which sufficiently controls metallic and particle contamination on the wafer is the technology that must be achieved as a prerequisite of device manufacturing. High-performance cleaning is also extremely important to ensure high yields in future mass production. In order to accomplish this goal, it is necessary to establish an even more advanced foundation for cleaning technology.

Controlling particle contamination in wafer cleaning is important to reduce defect density and improve device performance and yield. In this study, a screening experiment was employed to evaluate particle removal efficiency among different cleanings, including FSI BCLN, bench rinse and dry only, bench SC1/megasonic only, bench RCA cleaning, and bench RCA-based cleaning. To optimize particle removal efficiency in RCA-based cleaning, a design of experiment (DOE) has been done to investigate the impact of SC1/megasonic cleaning on Si3N4 particle removal efficiency. Bath temperature, megasonic power, and solution chemistry of SCI bath were evaluated. The removal efficiency in relations to particle sizes was also investigated

Photomask cleaning is getting important factor in whole mask process as device density is going to higher and introducing of P.S.M. Not only hard defect but contamination defects both on Qz and the Cr areas of photomask reticle can make problems on wafer. Especially contamination defect on the Cr of embedded type P.S.M. can cause the undesirable phase shift effect. Current method of photomask cleaning is not so improved compared to other areas of mask manufacturing. New technology of cleaning will be developed in near future but we try to figure out the limit of current cleaning method and maximize the current cleaning performance.

Modern wafer stepper generations are capable of realizinghigher circiut levels due to high-performance lenses in the WV region, but at the same time there is also the • necessity of designing assembly groups of the wafer stepper so that they meetthe requirements of a wide assortment range in modem device fabrication. Long years of practical experience in the use of steppers enabled Jenoptik to implement an new generation of wafer steppers, in whichparticular value was placed on the instrumental improvement of theparamemters:. interna] thermostatting/mininnim particle contamination— alignment accuracy - useful depth of focus. . I . INTRODUCTION Jenoptik JENA GmbEI looks back to a nearly 20-year-experience in the denel opment and producti on of photol ithography eiivs. During thisperiod about 500 photorepeaters and 230 wafer steppers were produced and on the basis of intergcrvernmentil agreements, mainly suppliedto the Comecon countries . Main trading partner of photol ithography

A serious, yield impacting defect was detected after polysilicon etch using the KLA-2028, an automated optical wafer inspection system. Visual inspection of the defect on a video monitor indicated that it was a resist particle. SEM analysis, however, showed that the defect was the result of resist pileup caused by particles. The source of these particles was traced to a wet station operation, but particle levels at the wet station were found to be at presumably acceptable levels. The product wafers were particularly susceptible to particle contamination due to the hydrophobicity following the wet operation. Several rinses to reduce particle adhesion were tested. A rinse of choline was found to decrease particle levels substantially and to increase yields on electrical defect monitor devices.

Control of contamination on the surface of wafers during the manufacture of state-of-the-art microcircuits is imperative if high yields are to be obtained. Hence, wafers are often cleaned using a modified RCA clean to remove organic, metallic and particle contamination prior to microcircuit manufacture. Recently, wafers obtained from a particular vendor were found to have heavy particle contamination after a modified RCA clean. The wafers were also found to have a hydrophobic surface indicating the presence of heavy organic contamination. Analysis of the wafer surface revealed that it was covered with film of a polydimethylsiloxane-like compound. The source of the compound was found to be a gasket in the storage boxes used to transport the wafers. This paper describes the methodology used to identify the source of the contaminant and the cleaning methods developed to eliminate the particle contamination which it caused.

In VLSI and ULSI wafer processing areas, the detection and control of particles in vacuum processing equipment is crucial for cost-effective manufacturing. This is true because of stringent requirements for low defectivity in order to achieve realistic yields and because more than half the operations are performed in vacuum environments. Sources of particles and the mechanisms of transferring them in vacuum are reviewed, along with the special problems related to each of the various processes. Comparisons are made of the equipment configurations, modes of operation, gas flows, operating pressures, pumping and venting cycles, and important processing parameters. Results of particle contamination studies in some of these vacuum systems are discussed.

Since the goal of extreme ultraviolet lithography is to produce circuit patterns with critical dimensions less than 65 nm, a key to its success will be to identify and minimize the major sources of image placement (IP) error at the wafer. Two sources of IP error are in-plane distortion (IPD) and out-of-plane deformation (OPD) of the patterned reticle during chucking in the exposure tool. Among the many possible causes of IPD and OPD is particle contamination. Small pieces of debris lodged between the reticle and chuck have the potential to distort the pattern that is transferred to the device wafer. Such distortions may consume an unduly large portion of the error budget allotted to image placement. In order to limit these IP errors, it is first necessary to gain a thorough understanding of the behavior of a particle trapped during the chucking process. This article describes the techniques that were used to study these trapped particles and their potential effects on pattern placement accuracy.

The level of particulate contamination deposited on a wafer surface during the ion implant process is a subject of great concern in the semiconductor industry. Particle performance requirements have become increasingly stringent in terms of both quantity and size of particles added during a process step. Recent studies have shown that the majority of particles being added to a wafer undergoing the implant process are added during its transition between atmospheric and high vacuum environments. This paper outlines the effects that various modifications to gas flow patterns within the vacuum lock have on particle contamination levels. Data will be presented which documents improvements achieved at particle sizes of 0.5 μm and larger.