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For digital applications, researchers are exploring the use of Tunnel Field-Effect Transistors (TFETs) as an alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). TFETs offer unique qualities that can be harnessed in digital applications. The presented work focuses on the Drain Engineering Dual Metal Gate based Charge Plasma TFET (DE-DMG-CP-TFET) and its ability to implement various logic functions utilizing 2D device simulations. This simulation refers to employing computational tools to analyze electronic devices in two spatial dimensions, considering parameters such as current-voltage characteristics, electric field analysis, and energy band diagrams. This simulation-based approach enables a comprehensive understanding of the device's operation under different conditions and facilitates the optimization of its performance. The simulations provide insights into the impact of design parameters, material properties, and device configurations on its functionality. By leveraging the ambipolar nature and gate-controlled tunneling capability of TFETs, compact logic functions can be realized by carefully designing the gate-source overlap and selecting an appropriate silicon body thickness. This research highlights the potential of TFETs in compact logic implementation and demonstrates the value of two-dimensional device simulations in understanding device behavior and optimizing performance. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic operations like OR, AND, NAND and NOR. Using a gate-source overlap (LOV) and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET. For digital applications, researchers are looking into Tunnel Field-Effect Transistors (TFETs) as possible substitute for MOSFETs. Utilizing two-dimensional device simulations, a Drain Engineering Dual Metal Gate-based Charge Plasma TFET (DE-DMG-CP-TFET) is presented to implement various logic functions. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic gates operation. Using a gate-source overlap and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET [ABSTRACT FROM AUTHOR]

Conventional digital LLC synchronous rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700-V high voltage and 6.6-kW high power directly due to the high dv/dt and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high-voltage SiC LLC converter. Based on the LLC equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional LLC performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional LLC charger was built. Compared to the conventional SR method, the LLC efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme. [ABSTRACT FROM AUTHOR]

The single gate driven series connected power device stack possesses the advantages of high compactness and low cost. However, research of its short circuit (SC) characteristic remains uncovered. This article fills this gap and points out that, with the single gate driver it has the potential of over-current limitation. Furthermore, based on it, an improved single gate driven silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfet) stack with strong antishort circuit fault capabilities is proposed. By adding auxiliary circuits to adjust the driving process of the single gate driver, the SiC mosfet stack can be automatically turned off in both SC conditions of fault under load and hard switch fault, while the normal working principle of the stack is not influenced. Neither active control nor overcurrent detection is required, which is the biggest merit of the proposed topology. Its design and analysis are presented in detail, followed by the validation by conducting simulations and experiments. [ABSTRACT FROM AUTHOR]

Wide-bandgap (WBG) power devices have better dynamic characteristics and higher working temperatures compared to traditional Si devices and are more suitable for high-frequency and high-voltage applications because of fast turn-on and turn-off speeds. The main obstacle for the use of WBG devices is the high-frequency oscillation (HF-Osc) in voltage and current during the switching process. In this article, a new method of predicting the SiC mosfet switching behavior (including HF-Osc and slow switching) is proposed. First, the models of nonlinear capacitances are improved and parasitic elements are taken into account for improving the RLC equivalent circuit of the mosfet switching transient. On this basis, the LC equivalent frequency is obtained. Then, a new method is proposed to obtain the SiC mosfet instantaneous frequency. The comparison between them in the time domain makes it possible to analyze the SiC mosfet switching behavior. The prediction method is verified using a CREE SiC mosfet via a double pulse test. Experimental and simulation results show that the prediction method is effective in describing the HF-Osc characteristics. The proposed method can be used to effectively improve the mosfet HF-Osc, which provides guidance for the application of SiC mosfets. [ABSTRACT FROM AUTHOR]

The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°. [ABSTRACT FROM AUTHOR]

Shallow trench isolation drain extended MOS (STI-DeMOS) devices, known for their superior gate oxide reliability under high drain voltages, are widely used for the integration of CMOS-compatible high-voltage devices. However, they offer moderate high-frequency performance that limits the use of these devices even in mid-band 5G applications. A novel island drain and a double-gate drain-extended MOS (IDDG DeMOS) device with improved high-frequency performance is proposed in this work. The proposed device has a core MOSFET and an STI-DeMOS with a self-aligned pocket well, both feature a shorter channel length than a typical STI-DeMOS device. The shorter gate length enhances the proposed device’s RF performance without degrading the breakdown voltage. We have performed simulations using a well-calibrated deck in the Sentaurus TCAD environment. We have shown an increase in the transit frequency from 25 GHz in STI-DeNMOS to 53 GHz in the proposed IDDG DeNMOS device, and from 11 to 31 GHz for a p-type device at a 65-nm technology node. This work also presents the well edge variation immunity of the proposed device. All these features are achieved in the mainstream SoC-compatible CMOS process flow without any additional fabrication mask or process complexity. [ABSTRACT FROM AUTHOR]

Achieving a self-aligned structure has been an essential key to the development of silicon-based MOSFET technology over the past several decades. However, it is usually challenging to achieve such self-alignment in layered material-based devices due to the lack of conventional doping processes such as ion implantation. In this work, we demonstrate an electrically defined self-aligned test structure using two partially overlapping top gates and a bottom gate in a WSe2/SnSe2 van der Waals (vdW) heterojunction. The test structure allows us to discern the properties of the heterojunction without any confounding series resistance effect arising from the WSe2/metal contact junction. By controlling the individual gates in the test structure, we reconfigurably achieve both p-type TFET operation with a minimum subthreshold slope < 60 mV/decade and n-type MOSFET operation. The structure will be useful to test self-aligned device operations in layered materials without the confounding effect of gate-dependent large contact resistance. [ABSTRACT FROM AUTHOR]

Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation of the particular sensitivity of trench-geometry devices when exposed to a negative gate-bias overstress, the specific conditions that drive this degradation, and its recovery by the application of a dc negative bias temperature stress. [ABSTRACT FROM AUTHOR]

In this work, the intentional insertion of slots in metal gate (MG) is introduced to solve the dishing issue for the double-diffused drain MOSFET (DDDMOSFET) fabrication. For traditional DDDMOSFET, the gate oxide layer in slots will be reserved to improve the device reliability, which requires an additional photomask to screen the gate/slot regions during the following sidewall formation and source/drain (S/D) implantation. This makes the process more complicated with increased cost. Without that additional photomask, it is proposed that the removal of gate oxide layer in slots can directly allow the floating S/D formation and the followed Ni silicidation there. It is demonstrated that such a novel process can not only relieve the MG dishing issue but can also effectively result in ~16% higher ON current and comparable OFF current for both N- and P-DDDMOSFETs without threshold voltage shift after applying electrical stress on gates. It is also revealed that the floating silicided S/Ds in slots have negligible influence on device breakdown characteristics. By saving one photomask, this work proposes a novel solution for the effective integration of core devices with very small feature sizes and high-voltage (HV) devices with large feature sizes in the same die, which is a common challenge for display driver chip fabrication using high- ${k}$ /MG (HK/MG) technology. [ABSTRACT FROM AUTHOR]

This article presents quick analytical prediction methods of switching loss, turn-on/off overvoltage, di/dt, and dv/dt for SiC metal–oxide–semiconductor field-effect transistor based on device datasheet. First, the switching process is analyzed and the simplification principles are discussed based on charge conservation and flux conservation. Second, the analytical equations of switching loss, turn-on/off overvoltage, di/dt, and dv/dt are derived. Third, experimental results under different operating conditions are presented to validate the proposed methods. It is found that the average prediction error is 10.11%. Finally, relationships between switching performance and different parameters, such as parasitic capacitance, parasitic inductance, dc-voltage, and load current, are analyzed and summarized based on the proposed prediction methods. [ABSTRACT FROM AUTHOR]

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs' correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs. [ABSTRACT FROM AUTHOR]

Narrow-channel accumulated body nMOSFET devices with p-type side gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (${V}_{\text {side}}$). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage (${V}_{t}$) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm $\times $ 78 nm (width $\times $ length) device shows SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and ${V}_{t}$ increasing from 0.42 to 0.61 V as the temperature is reduced from 400 to 100 K. ${V}_{t}$ can be adjusted from ~0.3 to ~1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using ${V}_{\text {side}}$. This high level of tunability allows electronic control of ${V}_{t}$ and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (<10−13 A). [ABSTRACT FROM AUTHOR]

[Display omitted] • Strain modulation mechanism on two-dimensional Te transistor was investigated. • Tensile/compressive strains to Te were relaxed by interfacial/stacked layer. • Synergistic effects of strain and crystallinity engineering were proposed. • Te transistor showed enhanced property with a high mobility of 12.05 cm2/V·s. • Te transistor exhibited excellent stability under long-term and PBS/NBS tests. Two-dimensional p-type material, tellurium (Te), has been of particular interest owing to its extraordinary electronic, optoelectronic, and thermoelectric properties. Here, we report a promising strategy to demonstrate enhanced performance Te transistor via strain modulation effect. The compressive and tensile strains were induced to the room-temperature-sputtered Te channel layer by stacking with various metal interfacial layers, followed by the strain relaxation and deoxidization effects caused by the deposition of the aluminum oxide via atomic layer deposition process. The strain engineering mechanism was comprehensively investigated by various characterizations, and both strain modulation and deoxidization-assisted crystallinity improvement were shown to synergistically enhance the charge transport of Te transistor. As a result, the improvement in the device performance with uniformity was clearly achieved, demonstrating the carrier mobility of 12.05 cm2/V·s, the threshold voltage of 0.09 V, and the subthreshold swing of 4.34 V/decade. This further results in the stable long-term operation over 28 days and excellent electrical stability under harsh negative and positive biasing conditions. Thus, this study presents a novel strategy of strain modulation for improving the performance of Te transistor, which has great potentials for complementary-metal–oxide–semiconductor logic circuits. [ABSTRACT FROM AUTHOR]

Gate-oxide degradation has been one of the critical reliability concerns of silicon carbide (SiC) metal–oxide–semiconductor-field-effect transistors (mosfets), which could be monitored through aging-sensitive parameters. In this article, an online gate-oxide degradation monitoring method for planar SiC mosfets is proposed by extracting gate charge time at a specific range of gate voltage. It is based on the findings that the input capacitances of planar SiC mosfets change significantly over gate-oxide degradation, which is theoretically analyzed and experimentally verified. The capacitance variations are converted into the gate charge time as the new aging-sensitive parameter. The new parameter measurement circuit is proposed and integrated into the gate driver module. The article results indicate that the new parameter varies noticeably with gate-oxide degradation and the difference of this parameter caused by junction temperature is much smaller than that caused by degradation. Besides, the parameter is immune to package degradation and load current. The condition monitoring method can be implemented online since the parameter is extracted during the off-state of SiC mosfet devices, which does not affect normal operation. The confirmatory experiment is carried out to verify the correctness of the proposed method. [ABSTRACT FROM AUTHOR]

This article introduces the negative feedback into the gate drive. It proposes a negative feedback active gate drive (NFAGD) for silicon carbide devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. An auxiliary P-channel mosfet is introduced to construct a negative feedback control mechanism. Due to the negative feedback mechanism, the proposed drive can automatically attenuate the disturbance from the complementary device of the phase-leg. Compared to conventional gate drives, the proposed drive can suppress the crosstalk without influencing the switching speed, thus enables coordinated optimization of gate voltage stability and switching behavior. This article analyzes the operation principle and then recommend the fundamental design principle for the proposed NFAGD. Finally, experiment results demonstrate the effectiveness of the proposed NFAGD. [ABSTRACT FROM AUTHOR]

For silicon carbide power mosfets, high dv/dt in switching may bring about a high level of electromagnetic interference. This letter shows that the dv/dt rate decreases at lower load currents. A dynamic dv/dt control strategy is then proposed for switching loss reduction in the whole operating range, by maintaining the dv/dt at the maximum acceptable level. The effectiveness of the proposed control strategy is verified by an experiment, showing that the total switching loss can be reduced by as much as 22% at 30% load. Furthermore, the simulation shows that a power loss reduction of 11.4% can be obtained for an electric vehicle converter which typically operates at light loads for most of the time. [ABSTRACT FROM AUTHOR]

A unified model for multigate negative capacitance transistors with self-heating effects (SHEs) is developed. With a metal–ferroelectric–insulator–semiconductor (MFIS) structure, thermal effects result in different temperature rises in the channel and ferroelectric layer. A gate control equation for the double-gate and gate-all-around MFIS structures is developed, on top of which both the current–voltage and charge–voltage characteristics are covered. The formulations describe dependences of ferroelectric layer thickness, with backward compatibility for MOSFETs. A unified thermal network is then proposed for SHE, capturing the essential physics of couplings between ferroelectric temperature and conduction current. The model has been verified with TCAD simulations and implemented for circuit simulations. [ABSTRACT FROM AUTHOR]

The threshold voltage (${V}_{\text {th}}$) instability induced by gate stress has always been a significant reliability issue for silicon carbide (SiC) MOSFET. The negative bias temperature instability (NBTI) of 4H-SiC p-channel MOSFET (pMOS) was studied experimentally at 200 °C and compared with that of 4H-SiC n-channel MOSFET (nMOS). It is shown that the ${V}_{\text {th}}$ drift of pMOS after 20 ks of negative stress −18 or −30 V is around twice that of nMOS. The behavior of the interface traps after stress is also analyzed quantitatively. It is concluded that the hole oxide traps are the dominant mechanism resulting in this large ${V}_{\text {th}}$ drift difference between pMOS and nMOS, and the interface traps have little contribution to the threshold voltage drift in this study. Moreover, in a double logarithmic plot, the ${V}_{\text {th}}$ recovery curves at a gate voltage of 0 V indicate that nMOS has a faster recovery than pMOS at the initial time. And the slope of ${V}_{\text {th}}$ recovery curve for pMOS becomes larger after 100 s. [ABSTRACT FROM AUTHOR]

This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is $2.6~\mu \text{W}$. In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates. [ABSTRACT FROM AUTHOR]

In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs. [ABSTRACT FROM AUTHOR]

The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional ${V}_{\text {TH}}$ shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future. [ABSTRACT FROM AUTHOR]

The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

While the theoretical maximum of the memory window $\Delta {V}_{t}$ in a ferroelectric field-effect transistor (FEFET) is $2{E}_{C}{t}_{F}$ , ${E}_{C}$ and ${t}_{F}$ being coercive field and FE thickness, respectively, experimentally $\Delta {V}_{t}$ is observed to be much less than that, even in the case of complete polarization switching in the ferroelectric layer. This occurs because trapped charges in the gate oxide stack partially or completely screen the ferroelectric polarization, only a fraction of which gets “electrostatically” reflected in the semiconductor channel. In this article, we provide a generalized experimental framework to quantify the efficiency of practical FEFETs in converting the switched ferroelectric polarization into the memory window. To that end, we propose three efficiency metrics: 1) switched ferroelectric polarization $\Delta {P}_{F}$ to memory window conversion ratio, $\eta _{MW}=\Delta {V}_{t}/\Delta {P}_{F}$ ; 2) switched ferroelectric polarization to the semiconductor charge ($\Delta {Q}_{S}$) conversion efficiency or the charge conversion efficiency $\eta _{c}=\Delta {Q}_{s}/\Delta {P}_{F}$ ; and 3) the ratio of memory window to the width of polarization versus gate voltage hysteresis characteristics ($\Delta {V}_{P}$) or the voltage conversation efficiency $\eta _{V}=\Delta {V}_{t}/\Delta {V}_{P}$. We measure and compare these efficiency metrics in n-type and p-type FEFETs, fabricated in different facilities by different groups. In all the cases, we find that the maximum values of memory window efficiency $(\eta _{MW})_{max}$ , charge conversion efficiency $(\eta _{c}$) $_{max}$ , and voltage conversion efficiency ($\eta _{V}$) $_{max}$ are in the range: 2.5–5.5 Vm2/C, 4%–10%, and 5%–20%, respectively. [ABSTRACT FROM AUTHOR]

A contact resistance (${R}_{c}$) becomes a major parasitic resistance in highly scaled modern semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising solution to reduce the ${R}_{c}$ , because its contact area is larger than that for the conventional top contact (TC) structure. Therefore, in this article, the electrical and thermal characteristics are widely investigated in vertically stacked gate-all-around (GAA) MOSFET with a WAC by using a 3-D technology computer-aided design (TCAD) simulation. First, compared with the TC, the WAC shows 1.74 times higher ON-state current. It is attributed in part to the low ${R}_{c}$ and in part to the low source–drain resistance (${R}_{\text {SD}}$). Furthermore, thermal resistance (${R}_{\text {th}}$) is also reduced by 9.73% in WAC, which improves self-heating effects (SHEs). Considering the results, it is expected that the WAC structure could be an attractive candidate to simultaneously improve device performance and reliability. [ABSTRACT FROM AUTHOR]

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications. [ABSTRACT FROM AUTHOR]

Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-on-insulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 $\mu \text{m}$. Thus, thermal time constants of ~760 ns, extracted from a variety of gate lengths, are correctly predicted. [ABSTRACT FROM AUTHOR]

This article introduces a 4 kV/120 A solid-state dc circuit breaker (DCCB) based on discrete SiC mosfets. The DCCB is designed in a five-layer tower structure. Each layer consists of a circular main conduction branch and an attached gate driver. There are two primary benefits of the proposed DCCB. First, it reduces conduction loss with multiple devices in parallel. Second, it achieves an ultrafast response speed with SiC mosfets. Moreover, the gate drivers of the DCCB are powered by a domino inductive power transfer (IPT) system. It achieves the load-independent constant-voltage output characteristics, which means the outputs are immune to load variations. An IPT system prototype is implemented to test the power transfer performance. At 500-kHz frequency, the total output power reaches 15.73 W, which is sufficient to power on five gate drivers, with a peak transfer efficiency of 75.4%. The IPT system is tested to power a 4 kV/120 A DCCB prototype. It validates that the DCCB is effective to turn off 120 A current within 3.5 μs. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively investigate the electrical properties of the 1200 V planner-gate 4H-SiC power metal–oxide–semiconductor field-effect transistors under the mechanical strains. Three kinds of strains, including the biaxial strain, uniaxial strain parallel to the gate channel, and uniaxial strain perpendicular to the gate channel, are applied using the wafer bending system. It is found that all kinds of compressive strains improve the drain current (Id) under the same gate voltage (Vg) and shift the threshold voltage (Vth) negatively, while the tensile strains decrease Id and shift Vth positively. The Vth shift mainly results from the strain modulated band structure in the poly-Si gate. Under the same overdrive gate voltage (Vov), biaxial strains merely change Id, while both the parallel and perpendicular uniaxial compressive strains enhance Id. The uniaxial compressive strain elevates the electron mobility in the inverted channel by repopulating more electrons into the valleys with a smaller conduction effective mass, which results in the current improvement. [ABSTRACT FROM AUTHOR]

The drain to gate capacitance (Miller capacitance) of SiC MOSFETs leads to the Miller effect during switching transients. The Miller capacitance in a phase-leg configuration causes the crosstalk, the interaction between the two complementary switches, and the Miller plateau during the switching transient. The Miller effect reduces the switching speed, reduces reliability, and increases electromagnetic interference. In this article, by injecting a mirror cancellation current, the effects of Miller capacitance are canceled. The proposed technique includes a two-stage sensing and injection network to compensate for the nonlinearity of the Miller capacitance. The proposed technique can suppress both positive and negative gate voltage spikes induced by the crosstalk and reduce the switching power loss with the increased switching speed. Because no external control signals are required in the proposed technique, it can work with almost all commercial gate drivers. The detailed design for this proposed technique is presented in this article. The proposed technique was validated with both simulations and experiments. [ABSTRACT FROM AUTHOR]

Complementary circuits based on organic electrochemical transistors (OECTs) are attractive for the development of inexpensive and disposable point‐of‐care bioelectronic devices. Ambipolar OECTs, which employ a single channel material, could decrease the fabrication complexity and manufacturing costs of such circuits. An ideal channel material for ambipolar OECTs should be electrochemically stable in aqueous environments, afford facile ion insertion for both cations and anions, and also facilitate high and balanced electron and hole transport. In this study, triethylene glycol functionalized diketopyrrolopyrrole (DPP)‐based polymer is proposed for the development of ambipolar OECTs. It is shown that DPP‐based OECTs have a high and comparable figure of merit for both n‐ and p‐type operations. Logic NOT, NAND, and NOR operations with corresponding complementary circuits constructed from identical DPP‐based OECT devices are demonstrated. This study is an important step toward the development of sophisticated complementary metal–oxide–semiconductor‐like logic circuits using single‐component OECTs. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) degradation is caused by radiation-induced charge buildup in oxides. Radiation hardening of silicon-on-insulator (SOI) devices with deep submicrometer nodes or nanonodes is mainly concerned with the field oxide and buried oxide. In this article, a back-channel adjustment technique for TID hardening is proposed. The technique is compatible with the 130-nm partially depleted silicon on an insulator (PDSOI) commercial process with no extra effort applied to the design. After testing the key electrical parameters and characterizing the radiation tolerance of the typical T-gate I/O nMOS devices, the results show that the radiation tolerance of the devices can reach more than 1 Mrad(Si) with the back-channel adjustment technique, and electrical performance is comparable to that of commercial process devices. [ABSTRACT FROM AUTHOR]

An advanced gate-stack design of ferroelectric (FE) transistors has been proposed and investigated for logic compatible program/erase voltage, better scalability, and suppressed depolarization field. The ferroelectric-metal (FeM) FinFET (FeM-FinFET) and stacked nanosheets transistor (FeM-Nanosheet), which have an FE layer on top of the transistor’s gate, could adjust the area ratio (AR) between the FE capacitor (${A}_{\text{FE}}$) and the MOS capacitor (${A}_{\text{MOS}}$) (AR = ${A}_{\text{FE}} / {A}_{\text{MOS}}$) using the floating gate between them, thereby enhancing the electric field on the FE layer. In particular, the proposed FeM-Nanosheet could have the flexibility to lower the operating voltage and depolarization field by increasing the number of nanosheets to reduce the AR. [ABSTRACT FROM AUTHOR]

Series connection of SiC power MOSFET is an attractive approach to expand the blocking voltage of SiC devices, whereas the dynamic voltage balancing among the series-connected devices is the most critical challenge of the technique. In this article, a simple, fast, and cost-effective dynamic voltage balancing circuit of the series-connected SiC MOSFETs is proposed to suppress the voltage imbalance among the devices. The proposed circuit is composed of a resistor-capacitor (RC) snubber with a coupled inductor to effectively sense the voltage imbalance and add a compensated signal to the gate driving voltage. In the article, the operation principle of the proposed method is described in detail and the parameter selection of the circuit is given. Then the optimized layout of the circuit in a typical half-bridge SiC power module is proposed to reduce the stray parameters introduced by the coupled inductor effectively. The proposed method is verified by experiments under different conditions. Compared with a purely RC snubber balancing strategy, the capacitor can be significantly reduced. Since only passive components are required in the feedback loop, the proposed method demonstrates a reliable and straightforward approach to achieve equal voltage sharing of the series-connected devices. [ABSTRACT FROM AUTHOR]

We propose a parallel negative-capacitance field-effect transistor (P-NCFET) structure, in which a ferroelectric operating in its negative-capacitance region is placed in parallel with the gate and source terminals of a MOSFET. The P-NCFET is stabilized by combining careful matching of the ferroelectric with the gate capacitance along with simple feedback realized using current mirrors. The novel stabilization approach opens the possibility for a variety of new applications that exploit the negative capacitance of ferroelectrics to cancel capacitance in integrated circuits. As an example, we show the P-NCFET structure has a significantly higher unity-current-gain frequency ${f}_{T}$ compared to a conventional MOSFET. [ABSTRACT FROM AUTHOR]

With the quasi-3-D scaling equation, quasi-3-D minimum channel potential, and drift-diffusion model, a unified subthreshold current model for junctionless multiple-gate (JLMG) MOSFETs including quadruple-gate (QG), triple-gate (TG), and omega-gate ($\Omega \text{G}$) devices is developed. With this subthreshold current model, the noise margin (NM) behavior of the subthreshold logic gate composed of JLMG MOSFETs is assessed. With the same cross-sectional area of the devices, the QG MOSFET provides the largest NM among the three devices due to its smallest scaling length. On the contrary, the TG MOSFET with the largest scaling length exhibits the smallest NM. The short-channel-degraded NM behavior can be similarly seen in these devices. In terms of design triangle (DT) of subthreshold logic gate, the QG MOSFET can provide the largest DT as opposed to the smallest one supplied by the TG device. The transistor strength balance (TSB) between p-type and n-type JLMG MOSFETs can be adjusted by tuning the gate work function to implement the optimum NM design. Finally, the impact of random doping fluctuation (RDF) on NM degradation is also discussed in this work. [ABSTRACT FROM AUTHOR]

The gate–bulk/body voltage ${V}_{\text {gb}}$ -dependent effect of the source or drain–bulk/body junction capacitance ${C}_{j}$ that is originated from the variation in the gate-edge sidewall junction area due to the modulation of the channel depletion depth in the OFF-state region of bulk/PD-SOI MOSFETs is physically revealed. This ${V}_{\text {gb}}$ -dependent ${C}_{j}$ is accurately extracted from the measured S-parameters and newly modeled in the wide off-bias range. The geometry-dependent model and parameter extraction method are proposed to make the new ${C}_{j}$ model applicable in SPICE. [ABSTRACT FROM AUTHOR]

We present and discuss explicit closed-form expressions for the saturation drain current of short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz–Krummenacher–Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert ${W}$ function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-current ratio, can be readily expressed as explicit functions of the terminal voltages. [ABSTRACT FROM AUTHOR]

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

We introduce the concept of constant-gate-charge scaling to increase the short-circuit withstand time of SiC power MOSFETs without increasing their ON-state resistance, gate charge, or oxide field. In gate-charge scaling, we scale the oxide thickness and gate drive voltage, keeping the oxide field constant. Short-circuit measurements on 1200 V SiC double-implanted MOSFETs (DMOSFETs) confirm that short-circuit withstand times can be increased by 2– $4\times $ without increasing ON-resistance, simply by reducing the oxide thickness and the gate drive voltage. [ABSTRACT FROM AUTHOR]

Macaroni channel structure is used popularly in 3-D NAND flash memory where the memory cells are connected in series. A model of inner potential in the subthreshold regime for the whole string of three transistors is presented and verified with the TCAD simulations. By using this model, the operation of the string and the interaction between transistors are investigated. Relative position dependence between transistors is also investigated. The obtained model can be used to predict the interference effect and be helpful in the design of the 3-D NAND flash memory cell. [ABSTRACT FROM AUTHOR]

Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. The main method for reducing the trench width is to design large trench angle. However large trench angle for better characteristics causes some challenges. And process window always becomes narrow to get excellent characteristic. For quality control of trench angle, we found that the wafer warpage was related to the trench angle at two process steps. We confirmed these mechanisms by simulation and experiment. Furthermore, we examined which process step was appropriate for monitoring the trench angle by wafer warpage. Finally, we acquired four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation. [ABSTRACT FROM AUTHOR]

In advanced field plate trench power MOSFETs (FP-MOSFETs), narrow and deep trench causes lots of challenges for process integration. Especially, process optimization for silicon in trench is the most crucial. Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. Therefore, we studied new process optimization of FP-MOSFETs with sequential phosphorus-doped silicon method, compared with “conventional” phosphorus diffusion method. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. Inserting 800°C annealing before 1000°C annealing contributed no voids in silicon field plates and gates. In addition, good electrical characteristics was demonstrated with the optimized process. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) MOSFETs still exhibit higher drifts of the threshold voltage than comparable silicon devices due to charge trapping, especially regarding small time scales. Understanding this behavior and the consequences in application relevant conditions is therefore of high research interest. Since charge trapping at different defects close to the SiC/ SiO2 interface and in the bulk oxide is strong bias and temperature-dependent, the phenomenon is referred to as bias temperature instability (BTI). It has been shown that drifts caused by BTI vary both in transient shape and magnitude for commercially available devices. These differences arise from defect densities and properties in the respective technologies. A physical model together with defect parameters that explain the charge transfer reactions at the defects is essential to understand all peculiarities of the transient degradation. In this work, we use a novel method to semiautomatically extract defect parameters within a two-state nonradiative multiphonon model framework. Our work reveals properties of defects responsible for shifts of the threshold voltage for both short-term ac and long-term dc stress conditions which are accurately reproduced for three different DMOS technologies. Our calibrated simulation framework is further used to extrapolate device degradation at operation relevant ac bias conditions to typical device lifetimes. [ABSTRACT FROM AUTHOR]

In this work, the influence of JFET region width on device’s performance and avalanche reliability is studied on 1200 V planar-gate silicon carbide (SiC) MOSFETs fabricated on a 4-in SiC wafer. Unclamped inductive switching (UIS) test is conducted to compare the devices under tests (DUTs) avalanche capability at both ${V}_{\text {GS}} ={0}$ V and ${V}_{\text {GS}} = -5$ V. At ${V}_{\text {GS}} ={0}$ V, the best avalanche reliability is achieved with a JFET region width of ${4}~\mu \text{m}$. Through mix-mode TCAD simulation, channel conduction is found to contribute to the failure at ${V}_{\text {GS}} ={0}$ V. While at ${V}_{\text {GS}} =-5$ V, the best avalanche reliability is achieved with a JFET region width ranging from 2 to ${3}~\mu \text{m}$. Hole injection is observed in the test and recognized in simulation, which critically influences the DUTs’ avalanche reliability at ${V}_{\text {GS}} = -5$ V. [ABSTRACT FROM AUTHOR]

An above-threshold I–V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source–drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the ${I}_{\text {ds}}-{V}_{\text {ds}}$ and ${I}_{\text {ds}}-{V}_{\text {gs}}$ characteristics generated by the model are shown to be consistent with TCAD simulations. [ABSTRACT FROM AUTHOR]

This article presents the experimental characterization of SiC MOSFETs exposed to heavy-ion irradiation. Different leakage paths related to the drain bias used during the tests are observed, suggesting different damage sites in the devices, which can be further verified through the post-irradiation measurements. TCAD simulations are utilized to explore the underlying failure mechanisms. Based on the evolution of the gate oxide field, it is shown that the damage first occurs in the middle of the JFET region, while gradually spreads to the channel region with the increase of drain bias, but terminates at the source region. A preliminary model to roughly emulate the drain bias dependence of such degradation behaviors is developed, and the simulation results match the experiments well. Additionally, the emission microscope (EMMI) is carried out so as to detect the latent damage at the die level. The findings in this article demonstrate that more attention should be paid to the damaged gate oxide induced by the heavy-ion strike before SiC MOSFETs could act as a drop-in replacement of Si-based counterparts in avionic applications. [ABSTRACT FROM AUTHOR]

To achieve lower specific ON-resistance (${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$), a novel accumulation lateral double-diffused MOSFET (ALDMOS) characterized by a convex-shaped field plate (CFP) structure is proposed and investigated experimentally. The CFP structure above the ${N}$ -drift region consists of two diodes, with its contact regions embedding into the drain and source region. Hence, the proposed device could shrink the drift length and utilize the drift region effectively to sustain the same level of breakdown voltage in the OFF-state. Furthermore, the CFP structure enables to form a continuous electron accumulation layer at the drift surface in the ON-state. Consequently, the proposed CFP ALDMOS could obtain an ultralow ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$ and achieve a better tradeoff relationship between BV and ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$. The experimental results show that the CFP ALDMOS realizes a BV of 448 V and ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$ of 16.9 $\text{m}\Omega \cdot $ cm2 with an extremely high figure of merit of 11.87 MW/cm2, decreasing ${R}_{{ \mathrm{\scriptscriptstyle ON},\text {SP}}}$ by 55.6% compared with theoretical triple-REduced SURface Field (RESURF) LDMOS at the same BV. [ABSTRACT FROM AUTHOR]

This article presents, for the first time, a study about of behavior of the intrinsic effects from diamond layout style [longitudinal corner effect (LCE) and PArallel connection of MOSFETs with Different channel Lengths Effect (PAMDLE)] for metal–oxide–semiconductor field-effect transistors (MOSFETs) influenced by wide high-temperature ranges. These effects are capable of boosting the electrical performance of analog MOSFETs in relation to that of the standard MOSFET (rectangular gate shape). First, we have developed an experimental comparative study between MOSFETs implemented with the hexagonal layout style diamond MOSFET (DM) and its rectangular MOSFET (RM) counterpart, regarding that they present the same channel width and gate area, operating in a wide high-temperature range (from 300 to 573 K). These devices were manufactured with the technology of bulk complementary MOS (CMOS) integrated circuits (ICs) of 180 nm. The experimental results have shown that DM has obtained a better electrical performance of analog MOSFETs than the one observed in RM counterpart (for example, gains of 67% for saturation drain current and 90% for the transconductance), regardless of temperatures in which they were exposed. 3-D numerical simulations were used to justify the better electrical performance of DMs due to the LCE and PAMDLE effects, in relation to one of the RM counterparts, by observing the behavior of electrostatic potentials, longitudinal electric fields, and drain current densities of the devices as the temperature increases. Besides, a study about the short-channel effect has shown that DM can suppress this effect more effectively than RM at room temperature due to a smaller reduction in effective channel length of DM. [ABSTRACT FROM AUTHOR]